# US 12,153,964 B2 · Configurable logic platform with reconfigurable processing circuitry

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- Number: US 12,153,964 B2
- Document ID: US12153964B2
- Status: Granted
- Kind: B2
- Application number: 18/394,944
- Filed: 2023-12-22
- Published: 2024-04-18
- Granted: 2024-11-26
- Earliest claimed: 2013-08-23
- Assignees: ThroughPuter, Inc.
- Applicants: ThroughPuter, Inc.
- Inventors: Mark Henrik Sandstrom
- Web page: https://patentgrep.com/patent/US12153964B2

## CPC

- G06F 9/5038: {considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups)}
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 8/656: while running
- G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals}
- G06F 15/173: using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F 15/80: comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15})
- G06F 2209/483: Multiproc
- G06F 2209/5021: Priority
- H04L 47/78: Architectures of resource allocation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A configurable logic platform may include a physical interconnect for connecting to a processing system, first and second reconfigurable logic regions, a configuration port for applying configuration data to the first and second reconfigurable logic regions, and a reconfiguration logic function accessible via transactions of the physical interconnect, the reconfiguration logic function providing restricted access to the configuration port from the physical interconnect. The platform may include a first interface function providing an interface to the first reconfigurable logic region and a second interface function providing an interface to the first reconfigurable logic region. The first and second interface functions may allow information to be transmitted over the physical interconnect and prevent the respective reconfigurable logic region from directly accessing the physical interconnect. The platform may include logic configured to apportion bandwidth of the physical interconnect among the interface functions.

## Claims

### Claim 1

A method of operating a system comprising a plurality of hardware-implemented manycore processors, each manycore processor comprising a plurality of reconfigurable processing cores, the method comprising:
receiving at the system a plurality of packet-based data streams;
performing a load-balancing function to distribute the plurality of received packet-based data streams among the plurality of manycore processors, wherein each of the plurality of manycore processors has a capability to concurrently process at least two of the received packet-based data streams; and
within each respective manycore processor of the plurality of manycore processors,
maintaining a correspondence with a respective task instance for each distributed stream of the plurality of packet-based data streams that is distributed to the respective manycore processor,
buffering data from at least a portion of each of the distributed streams in association with the respective task instance,
repetitively performing a hardware-based allocation of at least a portion of the plurality of reconfigurable processing cores of the respective manycore processor to one or more task instances of the respective task instances,
associating each respective task instance with at least one corresponding fast-access memory block and at least one corresponding slow-access memory block,
for one or more reconfigurable processing cores of the plurality of reconfigurable processing cores allocated to a given one of the respective task instances, providing hardware-controlled memory access to the at least one corresponding fast-access memory block and the at least one corresponding slow-access memory block,
providing hardware-controlled multiplexing of buffered data corresponding to the given one of the respective task instances to the one or more reconfigurable processing cores allocated to the given one of the respective task instances, and
executing a hardware-based application task on the one or more reconfigurable processing cores allocated to the given task instance, based on the buffered data corresponding to the given one of the respective task instances.

### Claim 2 (depends on 1)

The method of claim 1, wherein the hardware-controlled memory access to the at least one corresponding slow-access memory block comprises hardware-controlled data transfers between at least one region of the at least one corresponding fast-access memory block and the at least one corresponding slow-access memory block.

### Claim 3 (depends on 2)

The method of claim 2, wherein:
a connection to the slow-access memory blocks corresponding to each of the respective task instances is shared between all of the respective task instances; and
providing the hardware-controlled memory access to the slow-access memory blocks comprises hardware-controlled arbitration between access requests corresponding to the respective task instances.

### Claim 4 (depends on 1)

The method of claim 1, wherein performing the hardware-based allocation of the at least the portion of the plurality of reconfigurable processing cores comprises basing the hardware-based allocation at least in part on an availability of data requested by a given one of the respective task instances in the corresponding at least one fast-access memory block.

### Claim 5 (depends on 1)

The method of claim 1, wherein the at least one corresponding fast-access memory block is a random-access memory block.

### Claim 6 (depends on 1)

The method of claim 1, wherein performing the hardware-based allocation of the at least the portion of the plurality of reconfigurable processing cores comprises basing the hardware-based allocation at least in part on an amount of the buffered data corresponding to the one or more task instances.

### Claim 7 (depends on 1)

The method of claim 1, further comprising storing one or more program instructions applicable to a given one of the respective task instances in the at least one corresponding fast-access memory block associated with the given one of the respective task instances.

### Claim 8 (depends on 1)

The method of claim 1, wherein performing the load-balancing function comprises, for a new packet-based data stream that has not been assigned to a given one of the plurality of hardware-implemented manycore processors, selecting a destination manycore processor of the plurality of hardware-implemented manycore processors based at least in part on an amount of presently inactive resources at the destination manycore processor.

### Claim 9 (depends on 8)

The method of claim 8, wherein selecting the destination manycore processor is further based on a core entitlement level defined for an application associated with the new packet-based data stream.

### Claim 10 (depends on 1)

The method of claim 1, wherein performing the load-balancing function comprises, for a given packet arriving at the system that is associated with a given one of the plurality of packet-based data streams:
determining whether the given one of the plurality of packet-based data streams is already assigned to a given one of the plurality of hardware-implemented manycore processors; and
when the given one of the plurality of packet-based data streams is already assigned to a given one of the plurality of hardware-implemented manycore processors, forwarding the given packet to the given one of the plurality of hardware-implemented manycore processors, and
otherwise, assigning one of the plurality of hardware-implemented manycore processors to process the given one of the plurality of packet-based data streams based at least in part on respective capacities of two or more of the plurality of hardware-implemented manycore processors, and forwarding the given packet to the assigned one of the plurality of hardware-implemented manycore processors.

### Claim 11 (depends on 1)

The method of claim 1, wherein:
each of the plurality of hardware-implemented manycore processors comprises a Field-Programmable Gate Array (FPGA); and
the method further comprises, for each respective manycore processor of at least one of the plurality of hardware-implemented manycore processors, configuring one or more of the plurality of reconfigurable processing cores of the respective manycore processor to perform operations in support of a particular application task required for a given packet-based data stream.

### Claim 12 (depends on 1)

The method of claim 1, wherein buffering the data from the at least a portion of each of the distributed streams in association with the respective task instances comprises, by control hardware logic, buffering packet data corresponding to each respective task instance for individual first-in first-out access of that packet data.

### Claim 13 (depends on 1)

The method of claim 1, wherein the slow-access memory is a large capacity memory.

### Claim 14

A computing system comprising:
a plurality of hardware-implemented manycore processors; and
a load balancer configured to
receive a plurality of packet-based data streams, and
distribute the plurality of received packet-based data streams among the plurality of hardware-implemented manycore processors, wherein each of the plurality of hardware-implemented manycore processors has a capability to concurrently process at least two of the received packet-based data streams;
wherein each respective manycore processor of the plurality of hardware-implemented manycore processors comprises a plurality of reconfigurable processing cores, each respective manycore processor being configured to
maintain a correspondence with a respective task instance for each distributed stream of the plurality of packet-based data streams that is distributed to the respective manycore processor,
buffer data from at least a portion of each of the distributed streams in association with the respective task instance,
repetitively perform a hardware-based allocation of at least a portion of the plurality of reconfigurable processing cores of the respective manycore processor to one or more task instances of the respective task instances,
associate each respective task instance with at least one corresponding fast-access memory block, and at least one corresponding additional memory block from a large capacity memory,
for one or more reconfigurable processing cores of the plurality of reconfigurable processing cores allocated to a given one of the respective task instances, provide hardware-controlled memory access to the at least one corresponding fast-access memory block and the at least one corresponding additional memory block,
provide hardware-controlled multiplexing of buffered data corresponding to the given one of the respective task instances to the one or more reconfigurable processing cores allocated to the given one of the respective task instances, and
execute a hardware-based application task on the one or more reconfigurable processing cores allocated to the given task instance, based on the buffered data corresponding to the given one of the respective task instances.

### Claim 15 (depends on 14)

The computing system of claim 14, wherein the hardware-controlled memory access to the at least one corresponding additional memory block comprises hardware-controlled data transfers between at least one region of the at least one corresponding fast-access memory block and the at least one corresponding additional memory block.

### Claim 16 (depends on 15)

The computing system of claim 15, wherein:
a connection to the additional memory block corresponding to each of the respective task instances is shared between all of the respective task instances; and
providing the hardware-controlled memory access to the additional memory block comprises hardware-controlled arbitration between access requests corresponding to the respective task instances.

### Claim 17 (depends on 14)

The computing system of claim 14, wherein performing the hardware-based allocation of the at least the portion of the plurality of reconfigurable processing cores comprises basing the hardware-based allocation at least in part on the availability of data requested by a given one of the respective task instances in the at least one corresponding fast-access memory block.

### Claim 18 (depends on 14)

The computing system of claim 14, wherein the at least one corresponding fast-access memory block is a random-access memory block.

### Claim 19 (depends on 14)

The computing system of claim 14, wherein performing the hardware-based allocation of the at least the portion of the plurality of reconfigurable processing cores comprises basing the hardware-based allocation at least in part on an amount of the buffered data corresponding to the one or more task instances.

### Claim 20 (depends on 14)

The computing system of claim 14, further configured to store one or more program instructions applicable to a given one of the respective task instances in the at least one corresponding fast-access memory block associated with the given one of the respective task instances.

### Claim 21 (depends on 14)

The computing system of claim 14, wherein configured to distribute the plurality of received packet-based data streams comprises configured to, for a new packet-based data stream that has not been assigned to a given one of the plurality of hardware-based manycore processors, select a destination manycore processor of the plurality of hardware-based manycore processors based at least in part on an amount of presently inactive resources at the destination manycore processor.

### Claim 22 (depends on 21)

The computing system of claim 21, wherein selecting the destination manycore processor is further based on a core entitlement level defined for an application associated with the new packet-based data stream.

### Claim 23 (depends on 14)

The computing system of claim 14, wherein configured to distribute the plurality of received packet-based data streams comprises configured to, for a given packet arriving at the computing system that is associated with a given one of the plurality of packet-based data streams:
determine whether the given one of the plurality of packet-based data streams is already assigned to a given one of the plurality of hardware-implemented manycore processors; and
when the given one of the plurality of packet-based data streams is already assigned to a given one of the plurality of hardware-implemented manycore processors, forward the given packet to the given one of the plurality of hardware-implemented manycore processors, and
otherwise, assign one of the plurality of hardware-implemented manycore processors to process the given one of the packet-based data streams based at least in part on respective capacities of two or more of the plurality of hardware-implemented manycore processors, and forward the given packet to the assigned one of the plurality of hardware-implemented manycore processors.

### Claim 24 (depends on 14)

The computing system of claim 14, wherein each of the plurality of hardware-implemented manycore processors comprises a Field-Programmable Gate Array (FPGA), the computing system further configured to, for each respective manycore processor of at least one of the plurality of hardware-implemented manycore processors, configure one or more of the plurality of reconfigurable processing cores of the respective manycore processor to perform operations in support of a particular application task required for a given packet-based data stream.

### Claim 25 (depends on 14)

The computing system of claim 14, wherein buffering the data from the at least a portion of each of the distributed streams in association with the respective task instances comprises, by control hardware logic, buffering packet data corresponding to each respective task instance for individual first-in first-out access of that packet data.

### Claim 26 (depends on 14)

The computing system of claim 14, wherein the large capacity memory is a slow-access memory.