Virtualized multicore systems with extended instruction heterogeneity
AssigneeGoogle Inc.
InventorRussell C. Mckown
Life of this patent
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Abstract
A system on a chip may include a plurality of data plane processor cores sharing a common instruction set architecture. At least one of the data plane processor cores is specialized to perform a particular function via extensions to the otherwise common instruction set architecture. Such systems on a chip may have reduced physical complexity, cost, and time-to-market, and may provide improvements in core utilization and reductions in system power consumption.
Claims17
A computer-implemented method performed by a physical computing device, the computer-implemented method comprising:
- identifying a set of extended instructions of a common instruction set architecture (ISA) for processing a task which are executable by a first data plane processing core;
- trapping the set of extended instructions;
- determining equivalent processing instructions for the task from a different set of instructions of the common ISA which are executable by a second data plane processing core, wherein the different set of instructions are configured to generate computationally equivalent processing results as the trapped set of the extended instructions executable by the first data plane processing core which are not executable by the second data plane processing core;
- and
- executing, by the second data plane processing core, the equivalent processing instructions from the different set of instructions of the common ISA to produce computational results that are equivalent to the set of the extended instructions of the common ISA executable by the first data plane processing core.
A non-transitory computer-readable medium comprising instructions, that when executed by one or more processors, cause the one or more processors to perform:
- identifying a set of extended instructions of a common instruction set architecture (ISA) for processing a task which are executable by a first data plane processing core;
- trapping the set of extended instructions;
- determining equivalent processing instructions for the task from a different set of instructions of the common ISA which are executable by a second data plane processing core, wherein the different set of instructions are configured to generate computationally equivalent processing results as the trapped set of the extended instructions executable by the first data plane processing core which are not executable by the second data plane processing core;
- and
- executing, by the second data plane processing core, the equivalent processing instructions from the different set of instructions of the common ISA to produce computational results that are equivalent to the set of the extended instructions of the common ISA executable by the first data plane processing core.
A system comprising:
- one or more physical computing devices comprising memory, wherein the one or more physical computing devices are configured to:
- identify a set of extended instructions of a common instruction set architecture (ISA) for processing a task which are executable by a first data plane processing core;
- trap the set of extended instructions;
- determine equivalent processing instructions for the task from a different set of instructions of the common ISA which are executable by a second data plane processing core, wherein the different set of instructions are configured to generate computationally equivalent processing results as the trapped set of the extended instructions executable by the first data plane processing core which are not executable by the second data plane processing core;
- and
- execute, by the second data plane processing core, the equivalent processing instructions from the different set of instructions of the common ISA to produce computational results that are equivalent to the set of the extended instructions of the common ISA executable by the first data plane processing core.
Dependencies are inferred from the claim text.