Semiconductor device with composite gate dielectric and method for preparing the same
AssigneeNanya Technology Corporation
InventorLi-Han Lu
Life of this patent
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Abstract
A semiconductor device includes a first source/drain region and a second source/drain region disposed in a semiconductor substrate. The semiconductor device also includes a word line structure disposed in the semiconductor substrate and between the first source/drain region and the second source/drain region. The word line structure includes a composite gate dielectric, and a lower electrode layer disposed over the composite gate dielectric. The word line structure also includes an upper electrode layer disposed over the lower electrode layer, and a graphene layer disposed between the lower electrode layer and the upper electrode layer. The composite gate dielectric includes a gate dielectric layer and a protection liner.
Claims17
A semiconductor device, comprising:
- a first source/drain region and a second source/drain region disposed in a semiconductor substrate;
- and
- a word line structure disposed in the semiconductor substrate and between the first source/drain region and the second source/drain region, wherein the word line structure comprises:
- a composite gate dielectric including a gate dielectric layer and a protection liner;
- a lower electrode layer disposed over the composite gate dielectric;
- an upper electrode layer disposed over the lower electrode layer;
- and
- a first graphene layer disposed between the lower electrode layer and the upper electrode layer;
- a dielectric layer disposed over the semiconductor substrate and the word line structure;
- and
- a bit line structure disposed over the dielectric layer and the first source/drain region;
- wherein the bit line structure further comprises:
- an upper bit line layer disposed over the first composite conductive feature;
- and
- a second composite conductive feature disposed over the upper bit line layer.
A semiconductor device, comprising:
- a dielectric layer disposed over a semiconductor substrate;
- and
- a bit line structure disposed over the dielectric layer, wherein the bit line structure comprises:
- a lower bit line layer;
- an upper bit line layer disposed over the lower bit line layer, wherein the lower bit line layer and the upper bit line layer are made of different materials;
- and
- a first composite conductive feature disposed between the lower bit line layer and the upper bit line layer.
A semiconductor device, comprising:
- a word line structure disposed in a semiconductor substrate, wherein the word line structure comprises:
- a composite gate dielectric;
- a lower electrode layer disposed over the composite gate dielectric;
- an upper electrode layer disposed over the lower electrode layer, wherein the lower electrode layer and the upper electrode layer are made of different materials;
- and
- a first graphene layer disposed between the lower electrode layer and the upper electrode layer and surrounding the upper electrode layer;
- a first source/drain region and a second source/drain region disposed in the semiconductor substrate and at opposite sides of the word line structure;
- and
- a bit line structure disposed over the first source/drain region, wherein the bit line structure comprises:
- a lower bit line layer;
- a first composite conductive feature disposed over the lower bit line layer;
- an upper bit line layer disposed over the first composite conductive feature, wherein the lower bit line layer and the upper bit line layer are made of different materials;
- and
- a third graphene layer disposed over the upper bit line layer.
Dependencies are inferred from the claim text.