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US 12,149,207 B2Granted
High voltage digital power amplifier
AssigneeIntel Corporation
InventorsOfir Degani, Assaf Ben-Bassat, Ashoke Ravi, Ina Shternberg, Naor Shay
Life of this patent
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Abstract
Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg.
Claims24
A digital power amplifier circuit, comprising:
- a plurality of p-type transistors, a first one of the plurality of p-type transistors having a gate configured to be coupled to a first signal that varies between a first voltage range defined by a first upper voltage level and a first lower voltage level;
- a plurality of n-type transistors, a first one of the plurality of n-type transistors having a gate configured to be coupled to a second signal that varies between a second voltage range defined by a second upper voltage level and a second lower voltage level;
- and
- a pair of transistors coupled to a gate of a second one of the plurality of p-type transistors and to a second one of the plurality of n-type transistors to form a capacitive divider between (i) the pair of transistors, and (ii) the second one of the plurality of p-type transistors and the second one of the plurality of n-type transistors thereby defining a feedback capacitive ratio,
- wherein an output of the digital power amplifier circuit is configured to generate an output signal in accordance with the feedback capacitive ratio such that the output signal varies between a third voltage range defined by the first upper voltage level of the first signal and the second lower voltage level of the second signal.
2 more elements
A digital power amplifier driver cell, comprising:
- a set of p-type transistors including a first p-type transistor having a gate configured to be coupled to a first time-varying digital signal that varies between a first logic high voltage level and a first logic low voltage level;
- a set of n-type transistors including a first n-type transistor having a gate configured to be coupled to a second time-varying digital signal that varies between a second logic high voltage level and a second logic low voltage level;
- and
- a pair of transistors coupled to a gate of a second one of the set of p-type transistors and to a second one of the set of n-type transistors to form a capacitive divider between (i) the pair of transistors, and (ii) the second one of the set of p-type transistors and the second one of the set of n-type transistors thereby defining a feedback capacitive ratio,
- wherein an output of the digital power amplifier driver cell is configured to generate a time-varying digital output signal in accordance with the feedback capacitive ratio such that the time-varying digital output signal varies between the first logic high voltage level and the second logic low voltage level.
2 more elements
Dependencies are inferred from the claim text.