Memory system and memory operation
AssigneeSony Semiconductor Solutions Corporation
InventorsMidori Aizawa, Masami Kuroda, Haruko Takahashi
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Abstract
A memory system according to an aspect of the present disclosure includes a soft error generator that generates write data or read data considering a probability error by using a specific number as a random number. In the memory system, the write data or the read data considering a probability error is generated by using the random number. Herein, whether or not an error occurs is randomly changed depending on the random number. Accordingly, an error stochastically occurs, which makes it possible to reproduce a soft error.
Claims12
A memory system, comprising:
- a bit line selector;
- a soft error generator configured to generate one of write data or read data based on a probability error and a specific number;
- and
- a writing controller configured to output, at a specific timing, the write data to the bit line selector, wherein the bit line selector is configured to store the write data in a specific address of a memory based on a specific voltage.
A memory system, comprising:
- a bit line selector;
- a first soft error generator configured to generate write data based on a first probability error and a first number;
- a second soft error generator configured to generate read data based on a second probability error and a second number;
- and
- a writing controller configured to output, at a specific timing, the write data to the bit line selector, wherein the bit line selector is configured to store the write data in a specific address of a memory based on a specific voltage.
A non-transitory computer-readable medium having stored thereon, computer-executable instructions which, when executed by a processor, cause the processor to execute operations, the operations comprising:
- generating one of write data or read data based on a probability error and a specific number;
- outputting the write data at a specific timing;
- and
- storing the write data in a specific address of a memory based on a specific voltage.
A non-transitory computer-readable medium having stored thereon, computer-executable instructions which, when executed by a processor, cause the processor to execute operations, the operations comprising:
- generating write data based on a first probability error and a first number;
- generating read data based on a second probability error and a second number;
- outputting the write data at a specific timing;
- and
- storing the write data in a specific address of a memory based on a specific voltage.
Dependencies are inferred from the claim text.