Non-volatile memory cell with single poly, floating gate extending over two wells

A non-volatile memory array, comprising:

• a pair of non-volatile memory cells, each non-volatile memory cell having:
• a first body and a second body,
• a storage transistor in the first body having a first conduction region and a second conduction region delimited by a channel region,
• a control gate region in the second body,
• a single floating gate region embedded in an insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and the second portion being connected and electrically coupled,
• a first selection via, a second selection via, and a third selection via configured to electrically couple the first conduction region through a first conduction node to a source line, the second conduction region through a second conduction node to a bit line, and the control gate region through a first control node coupled to a word line shared between the pair of non-volatile memory cells, respectively,
• wherein the pair of non-volatile memory cells are configured to be separately erased by applying a first erase voltage and a second erase voltage to the first conduction region and the control gate region respectively, and
• wherein, by applying the first erase voltage and the second erase voltage, an erase voltage drop is generated between the second portion and the control gate region and a tunneling current flows between the control gate region and the second portion by Fowler-Nordheim effect.

A non-volatile memory array, comprising:

• a pair of non-volatile memory cells, each non-volatile memory cell having:
• a first body and a second body,
• a storage transistor in the first body having a first conduction region and a second conduction region delimited by a channel region,
• a control gate region in the second body,
• a single floating gate region embedded in an insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and the second portion being connected and electrically coupled,
• a first selection via, a second selection via, and a third selection via configured to electrically couple the first conduction region through a first conduction node to a source line, the second conduction region through a second conduction node to a bit line, and the control gate region through a first control node coupled to a word line shared between the pair of non-volatile memory cells, respectively,
• wherein the pair of non-volatile memory cells are configured to be separately erased by applying a first erase voltage and a second erase voltage to the first conduction region and the control gate region, respectively,
• wherein, by applying the first erase voltage and the second erase voltage, an erase voltage drop is generated between the second portion and the control gate region and a tunneling current flows between the control gate region and the second portion by Fowler-Nordheim effect,
• wherein the pair of non-volatile memory cells are configured to be programmed together by applying a first programming voltage, a second programming voltage, and a third programming voltage to the first conduction region, the control gate region, and the second body of each of the non-volatile memory cells, respectively, and
• wherein, by applying the first, second, and third programming voltages, a voltage drop is generated between the second portion and the control gate region, a breakdown current flows between the control gate region and the second body, and electrical charges in the breakdown current are injected from the second body into the second portion by Band-to-Band Hot Electron Injection effect.