Work stealing in heterogeneous computing systems

At least one non-transitory machine-readable medium comprising instructions to cause at least one first processor circuit of a first type to at least:

• encode first and second index ranges of a data parallel operation;
• allocate a first task from a workload to a first work queue corresponding to the first processor circuit;
• and
• move a second task to the first work queue from a second work queue corresponding to a second processor circuit of a second type, the first processor circuit and the second processor circuit corresponding to a work-group, the move after a determination that the first processor circuit is a leader in the work-group, the move based on load balancing and at least one of processing speed or reduced power consumption, the move atomically performed via a read operation and a write operation to update a pointer of the second work queue in a same bus cycle to prevent multiple entities from moving the second task in the same bus cycle.

A method comprising:

• obtaining tasks from a workload by encoding first and second index ranges of a data parallel operation;
• allocating a first task from the workload to a first work queue corresponding to first computation circuitry of a first type;
• allocating a second task from the workload to a second work queue corresponding to second computation circuitry of a second type;
• and
• moving the second task from the second work queue to the first work queue via an atomic operation, the first computation circuitry and the second computation circuitry corresponding to a work-group, the moving after a determination that the first computation circuitry is a leader in the work-group, the atomic operation to perform a read operation and a write operation to update a pointer of the second work queue in a same bus cycle during the moving of the second task, the atomic operation to prevent multiple entities from moving the second task in the same bus cycle, the moving of the second task based on load balancing and at least one of processing speed or reduced power consumption.

An apparatus comprising:

• interface circuitry;
• machine-readable instructions;
• and
• at least one processor circuit to be programmed by the machine-readable instructions to:
• allocate a first task to a first work queue of a first one of the at least one processor circuit corresponding to a first type of circuitry;
• allocate a second task to a second work queue of a second processor circuit corresponding to a second type of circuitry;
• determine to re-allocate the second task from the second work queue to the first work queue after a determination that the first one of the at least one processor circuit is a leader of a work-group that includes the second processor circuitry and the first one of the at least one processor circuit;
• and
• re-allocate the second task from the second work queue to the first work queue based on load balancing and at least one of processing speed or reduced power consumption, the re-allocating including a read operation and a write operation performed atomically to update a pointer of the second work queue in a same bus cycle to prevent multiple entities from re-allocating the second task before completing the re-allocating.