Sharding for synchronous processors
AssigneeGoogle Inc.
InventorsReiner Pope, Herman Schmit, Michial Allen Gunter
Life of this patent
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Abstract
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for sharding dataflow graphs for a device having multiple synchronous tiles. One of the methods includes receiving a representation of a dataflow graph comprising a plurality of nodes that each represent respective matrix operations to be performed by a device having a plurality synchronous tiles. Candidate allocations of respective portions of the dataflow graph to each tile of the plurality of synchronous tiles are evaluated according to one or more resource constraints of the device. One of the candidate allocations is selected based on evaluating each candidate allocation.
Claims20
A system comprising:
- one or more computers and one or more storage devices storing instructions that are operable, when executed by the one or more computers, to cause the one or more computers to perform operations comprising:
- receiving a representation of a dataflow graph comprising a plurality of nodes, wherein each node of the plurality of nodes represents respective matrix operations to be performed by a hardware integrated circuit comprising a plurality of synchronous tiles;
- generating a plurality of candidate allocations of respective portions of the dataflow graph to each synchronous tile of the plurality of synchronous tiles;
- evaluating each candidate allocation of the plurality of candidate allocations according to one or more resource constraints of the hardware integrated circuit;
- selecting a candidate allocation of the plurality of candidate allocations in response to evaluating each candidate allocation of the plurality of candidate allocations;
- and
- generating, based on the selected candidate allocation of the plurality of candidate allocations, hardware instructions for executing, at the hardware integrated circuit, a matrix operation represented by a node of the plurality of nodes of the dataflow graph.
A computer-implemented method comprising:
- receiving a representation of a dataflow graph comprising a plurality of nodes, wherein each node of the plurality of nodes represents respective matrix operations to be performed by a hardware integrated circuit comprising a plurality of synchronous tiles;
- generating a plurality of candidate allocations of respective portions of the dataflow graph to each synchronous tile of the plurality of synchronous tiles;
- evaluating each candidate allocation of the plurality of candidate allocations according to one or more resource constraints of the hardware integrated circuit;
- selecting a candidate allocation of the plurality of candidate allocations in response to evaluating each candidate allocation of the plurality of candidate allocations;
- and
- generating, based on the selected candidate allocation of the plurality of candidate allocations, hardware instructions for executing, at the hardware integrated circuit, a matrix operation represented by a node of the plurality of nodes of the dataflow graph.
A non-transitory computer storage medium encoded with a computer program, the computer program comprising instructions that are executable by a data processing apparatus to cause performance of operations comprising:
- receiving a representation of a dataflow graph comprising a plurality of nodes, wherein each node of the plurality of nodes represents respective matrix operations to be performed by a hardware integrated circuit comprising a plurality of synchronous tiles;
- generating a plurality of candidate allocations of respective portions of the dataflow graph to each synchronous tile of the plurality of synchronous tiles;
- evaluating each candidate allocation of the plurality of candidate allocations according to one or more resource constraints of the hardware integrated circuit;
- selecting a candidate allocation of the plurality of candidate allocations in response to evaluating each candidate allocation of the plurality of candidate allocations;
- and
- generating, based on the selected candidate allocation of the plurality of candidate allocations, hardware instructions for executing, at the hardware integrated circuit, a matrix operation represented by a node of the plurality of nodes of the dataflow graph.
Dependencies are inferred from the claim text.