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US 12,147,783 B2Granted
Pipelined hardware to accelerate modular arithmetic operations
AssigneeInternational Business Machines Corporation
InventorRajat Rao
Life of this patent
Estimating the term…
Abstract
Embodiments are directed to elliptic curve cryptography scalar multiplications in a generic field with heavy pipelining between field operations. A bit width is determined of operands in data to be processed by a modular hardware block. It is checked whether the bit width of the operands matches a fixed bit width of the modular hardware block. In response to there being a match, the modular hardware block processes the operands. In response to there being a mismatch, the operands are modified to be accommodated by the fixed bit width of the modular hardware block.
Claims20
A computer-implemented method comprising:
- determining a bit width of operands in data to be processed by a modular hardware block;
- and
- in response to there being a mismatch between the bit width of the operands and a fixed bit width of the modular hardware block, modifying the operands to be accommodated by the fixed bit width of the modular hardware block and causing the modular hardware block to process the operands, wherein:
- the modular hardware block comprises a first multiplication accumulator connected in series to a second multiplication accumulator such that the second multiplication accumulator is connected in series to a third multiplication accumulator, the first and second multiplication accumulators being connected to a correction block;
- performing, by the first multiplication accumulator, a first operation in order to output first high order bits to the second multiplication accumulator and output first low order bits to the correction block;
- performing, by the second multiplication accumulator, a second operation in order to output second high order bits to the third multiplication accumulator;
- and
- performing by the third multiplication accumulator, a third operation in order to output third low order bits to the correction block.
5 more elements
A system comprising:
- a memory having computer readable instructions;
- and
- one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
- determining a bit width of operands in data to be processed by a modular hardware block;
- in response to there being a mismatch between the bit width of the operands and a fixed bit width of the modular hardware block, modifying the operands to be accommodated by the fixed bit width of the modular hardware block and causing the modular hardware block to process the operands, wherein:
- the modular hardware block comprises a first multiplication accumulator connected in series to a second multiplication accumulator such that the second multiplication accumulator is connected in series to a third multiplication accumulator, the first and second multiplication accumulators being connected to a correction block;
- performing, by the first multiplication accumulator, a first operation in order to output first high order bits to the second multiplication accumulator and output first low order bits to the correction block;
- performing by the second multiplication accumulator, a second operation in order to output second high order bits to the third multiplication accumulator;
- and
- performing, by the third multiplication accumulator, a third operation in order to output third low order bits to the correction block.
7 more elements
A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform operations comprising:
- determining a bit width of operands in data to be processed by a modular hardware block;
- and
- in response to there being a mismatch between the bit width of the operands and a fixed bit width of the modular hardware block, modifying the operands to be accommodated by the fixed bit width of the modular hardware block and causing the modular hardware block to process the operands, wherein:
- the modular hardware block comprises a first multiplication accumulator connected in series to a second multiplication accumulator such that the second multiplication accumulator is connected in series to a third multiplication accumulator, the first and second multiplication accumulators being connected to a correction block;
- performing, by the first multiplication accumulator, a first operation in order to output first high order bits to the second multiplication accumulator and output first low order bits to the correction block;
- performing, by the second multiplication accumulator, a second operation in order to output second high order bits to the third multiplication accumulator;
- and
- performing, by the third multiplication accumulator, a third operation in order to output third low order bits to the correction block.
5 more elements
A computer-implemented method of forming a modular hardware block for scalar multiplication, the method comprising:
- connecting a first multiplication accumulator in series to a second multiplication accumulator such that the second multiplication accumulator is connected in series to a third multiplication accumulator;
- and
- connecting an input of a correction block to the first and third multiplication accumulators, wherein:
- the first multiplication accumulator performs a first operation in order to output first high order bits to the second multiplication accumulator and output first low order bits to the correction block;
- the second multiplication accumulator performs a second operation in order to output second high order bits to the third multiplication accumulator;
- and
- the third multiplication accumulator performs a third operation in order to output third low order bits to the correction block.
4 more elements
A modular hardware block for scalar multiplication, the modular hardware block comprising:
- a first multiplication accumulator connected in series to a second multiplication accumulator such that the second multiplication accumulator is connected in series to a third multiplication accumulator and each of the first, second, and third multiplication accumulators comprising a multiplication block coupled to an accumulator block, the multiplication block having a fixed bit width;
- a correction block coupled to the first and third multiplication accumulators;
- a data array coupled to the first multiplication accumulator and the correction block;
- and
- a module coupled to the data array, the module being configured to modify data to be accommodated by the fixed bit width, wherein:
- the first multiplication accumulator performs a first operation in order to output first high order bits to the second multiplication accumulator and output first low order bits to the correction block;
- the second multiplication accumulator performs a second operation in order to output second high order bits to the third multiplication accumulator;
- and
- the third multiplication accumulator performs a third operation in order to output third low order bits to the correction block.
6 more elements
Dependencies are inferred from the claim text.