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US 12,147,346 B2Granted
Method and apparatus for shared virtual memory to manage data coherency in a heterogeneous processing system
AssigneeIntel Corporation
InventorAltug Koker
Life of this patent
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Abstract
Embodiments described herein provide a scalable coherency tracking implementation that utilizes shared virtual memory to manage data coherency. In one embodiment, coherency tracking granularity is reduced relative to existing coherency tracking solutions, with coherency tracking storage memory moved to memory as a page table metadata. For example and in one embodiment, storage for coherency state is moved from dedicated hardware blocks to system memory, effectively providing a directory structure that is limitless in size.
Claims20
A heterogeneous computing device comprising:
- a graphics processor coupled with an application processor, wherein the graphics processor and the application processor each include a cache memory and first circuitry to perform virtual to physical memory address translation for a unified virtual memory system including a common virtual memory address space in which a complete virtual address space of the graphics processor is shared with the application processor;
- and
- wherein the first circuitry is to manage cache coherency state concurrently with virtual to physical memory address translation for an address in the unified virtual memory system and, concurrently with an address translation associated with a write to a virtual memory address of a block of memory, the first circuitry is to:
- determine a cache coherency state for a cache line associated with the block of memory based on cache coherency metadata stored contiguously with virtual to physical memory address translation data for the block of memory, the coherency ownership and the virtual to physical memory address translation data determined via a single read operation that is performed based on the virtual memory address of the block of memory;
- and
- based on the cache coherency state, determine coherency ownership for the cache line;
- and
- based on the coherency ownership, transfer the coherency ownership for the cache line between the graphics processor and the application processor.
5 more elements
A method of managing data coherency in a heterogeneous processing system, the method comprising
- performing a virtual to physical memory address translation for a memory write request to a block of memory having a virtual memory address in a unified virtual memory address space in which a complete virtual address space of a graphics processor is shared with an application processor;
- concurrently with the virtual to physical memory address translation, determining coherency ownership associated with the block of memory based on cache coherency metadata stored contiguously with virtual to physical memory address translation data for the block of memory, the coherency ownership and the virtual to physical memory address translation data determined via a single read operation that is performed based on the virtual memory address of the block of memory, wherein the block of memory is accessible to the graphics processor and the application processor via the virtual memory address;
- and
- transferring coherency ownership associated with the block of memory between the graphics processor and the application processor.
1 more element
A heterogeneous processing system comprising:
- a graphics processor including a first cache memory and a first circuit, the first circuit to perform virtual to physical memory address translation and manage cache coherency metadata;
- an application processor including a second cache memory and a second circuit, the second circuit to perform virtual to physical memory address translation and manage cache coherency metadata;
- a third cache memory coupled to the graphics processor and the application processor, the third cache memory to cache data in a block of memory shared between the graphics processor and the application processor, wherein the graphics processor and the application processor have a unified virtual memory system including a common virtual memory address space in which a complete virtual address space of the graphics processor is shared with the application processor;
- system memory coupled to the third cache memory, the system memory to store a page table including a virtual to physical memory address mapping for the common virtual memory address space and the cache coherency metadata, the cache coherency metadata stored contiguously with the virtual to physical memory address mapping, the cache coherency metadata including coherency ownership information for one or more cache lines associated with the block of memory;
- and
- wherein in association with a write request to the block of memory by the application processor or the graphics processor, the first circuit or the second circuit is to:
- perform a virtual to physical memory address translation for a virtual memory address of the block of memory based on an entry in the virtual to physical memory address mapping;
- concurrently with the virtual to physical memory address translation, determine coherency ownership associated with the block of memory via a single read operation that is performed based on the virtual memory address of the block of memory;
- and
- transfer coherency ownership associated with the block of memory between the graphics processor and the application processor.
7 more elements
Dependencies are inferred from the claim text.