Adaptive mode imbalance compensation
AssigneeAeonsemi, Inc.
InventorKy-Anh Tran
Life of this patent
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Abstract
Methods and apparatus for reducing mode conversion associated with differential signals are disclosed. An example method includes providing a common mode dither signal between a first terminal and a second terminal associated with a differential signal, generating a correlation signal representing a correlation of the common mode dither signal and the differential signal, and selectively incrementing a first capacitive loading at the first terminal or a second capacitive loading at the second terminal based at least in part on the correlation signal.
Claims18
A method for reducing mode conversion in a differential signal, the method comprising:
- providing a common mode dither signal between a first terminal and a second terminal associated with the differential signal;
- generating a correlation signal representing a correlation of the common mode dither signal and the differential signal;
- and
- selectively incrementing a first capacitive loading at the first terminal or a second capacitive loading at the second terminal based at least in part on the correlation signal, wherein selectively incrementing the first capacitive loading or the second capacitive loading comprises generating an average of the correlation signal and incrementing the first capacitive loading or the second capacitive loading based on a sign of the average of the correlation signal.
A mode conversion reduction circuit for a differential signal, comprising:
- a first terminal and a second terminal associated with the differential signal;
- a common mode dither signal generator to provide a common mode dither signal between the first terminal and the second terminal;
- a correlator to generate a correlation signal representing a correlation of the common mode dither signal and the differential signal;
- a first variable capacitance coupled to the first terminal, the first variable capacitance being based at least in part on the correlation signal;
- and
- a second variable capacitance coupled to the second terminal, the second variable capacitance being based at least in part on the correlation signal;
- wherein the first variable capacitance and the second variable capacitance are each based on a sign of an average value of the correlation signal.
A mode conversion reduction circuit, comprising:
- means for providing a common mode dither signal between a first terminal and a second terminal associated with a differential signal;
- means for generating a correlation signal representing a correlation of the common mode dither signal and the differential signal;
- and
- means for selectively incrementing a first capacitive loading at the first terminal or a second capacitive loading at the second terminal based at least in part on the correlation signal, wherein the means for selectively incrementing the first capacitive loading or the second capacitive loading comprises means for generating an average of the correlation signal and incrementing the first capacitive loading or the second capacitive loading based on a sign of the average of the correlation signal.
Dependencies are inferred from the claim text.