Pulse width modulation generated by a sigma delta loop

A sigma delta (SD) pulse-width modulation (PWM) loop, comprising:

• a loop filter implementing a linear transfer function to generate a loop filter signal, wherein the loop filter is configured to receive an input signal and a first feedback signal and generate the loop filter signal based on the input signal, the first feedback signal, and the linear transfer function;
• and
• a hysteresis comparator coupled to an output of the loop filter, the hysteresis comparator configured to receive the loop filter signal and generate a sigma delta PWM signal based on the loop filter signal,
• wherein the first feedback signal is derived from the sigma delta PWM signal,
• wherein the loop filter comprises a combiner circuit configured to receive the input signal and the sigma delta PWM signal, and generate a combined signal having a combined value that corresponds to a subtraction of the sigma delta PWM signal from the input signal, and
• wherein the hysteresis comparator is configured to receive the loop filter signal and generate the sigma delta PWM signal based on comparing the loop filter signal to a first hysteresis threshold and to a second hysteresis threshold, wherein the first hysteresis threshold is greater than a maximum amplitude of the input signal.