Signal envelope detector, overload detector, receiver, base station and mobile device
AssigneeIntel Corporation
InventorsMartin Clara, Giacomo Cascio
Life of this patent
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AssigneeIntel Corporation
InventorsMartin Clara, Giacomo Cascio
Estimating the term…
A signal envelope detector is provided. The signal envelope detector includes an input node configured to receive an input signal. Further, the signal envelope detector includes a capacitive voltage divider coupled to the input node and configured to generate an attenuated input signal by voltage division of the input signal. The signal envelope detector additionally includes a source follower transistor coupled between a first node configured to receive a first voltage supply signal and a second node configured to receive a second voltage supply signal. A gate terminal of the source follower transistor is coupled to the capacitive voltage divider and configured to receive the attenuated input signal. The signal envelope detector includes a rectifier circuit configured to receive and rectify an output signal of the source follower transistor. In addition, the signal envelope detector includes a low-pass filter coupled to the rectifier circuit and configured to generate an envelope signal indicative of a rectified envelope of the input signal by low-pass filtering of an output signal of the rectifier circuit.
A signal envelope detector, comprising:
Dependencies are inferred from the claim text.