Gallium Nitride high-electron mobility transistors with p-type layers and process for making the same
AssigneeWolfspeed, Inc.
InventorSaptharishi Sriram
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Abstract
A high-electron mobility transistor includes a substrate layer, a first buffer layer provided on the substrate layer, a barrier layer provided on the first buffer layer, a source provided on the barrier layer, a drain provided on the barrier layer, and a gate provided on the barrier layer. The transistor further includes a p-type material layer having a length parallel to a surface of the substrate layer over which the first buffer layer is provided, the length of the p-type material layer being less than an entire length of the substrate layer. The p-type material layer is provided in one of the following: the substrate layer, or the first buffer layer. A process of making the high-electron mobility transistor is disclosed as well.
Claims32
A high-electron mobility transistor comprising:
- a substrate layer;
- a buffer layer arranged on the substrate layer;
- a barrier layer arranged on the buffer layer;
- a drain arranged on the barrier layer;
- a gate arranged on the barrier layer;
- a source arranged on the barrier layer;
- the source and the drain being configured such that an electric current flows between the source and the drain via a two-dimensional electron gas (2DEG) induced at an heterointerface between the buffer layer and the barrier layer when the gate is biased at an appropriate level;
- and
- a p-type material layer arranged on the substrate layer below the barrier layer and the p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p-type material layer parallel to the surface of the substrate layer extends at least from the source toward the gate such that the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the substrate layer,
- wherein the p-type material layer extends 0% to 20%, 20% to 40%, 40% to 60%, or 60% to 80% of a gate length past a proximal edge of the gate;
- and
- wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
A process of making high-electron mobility transistor comprising:
- providing a substrate layer;
- arranging a buffer layer on the substrate layer;
- arranging a barrier layer arranged on the buffer layer;
- arranging a source on the barrier layer;
- arranging a drain on the barrier layer;
- arranging a gate on the barrier layer;
- configuring the source and the drain such that an electric current flows between the source and the drain via a two-dimensional electron gas (2DEG) induced at an heterointerface between the buffer layer and the barrier layer when the gate is biased at an appropriate level;
- and
- arranging a p-type material layer on the substrate layer below the barrier layer and the p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p-type material layer parallel to the surface of the substrate layer extends at least from the source toward the gate such that the p-type material layer is not located at least along a vertical axis of the drain perpendicular to the surface of the substrate layer,
- wherein the p-type material layer extends 0% to 20%, 20% to 40%, 40% to 60%, or 60% to 80% of a gate length past a proximal edge of the gate;
- and
- wherein the proximal edge of the gate is located on the barrier layer and on a source side of the gate.
Dependencies are inferred from the claim text.