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US 12,142,309 B2Granted
Low resistance MTJ antifuse circuitry designs and methods of operation
AssigneeEverspin Technologies, Inc.
InventorSyed M. Alam
Life of this patent
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Abstract
The present disclosure is drawn to, among other things, an antifuse circuit. The antifuse circuit includes a plurality of antifuse bitcells and a reference resistor. Each antifuse bitcell includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.
Claims20
An antifuse circuit, comprising:
- a plurality of magnetoresistive tunnel junction (MTJ) antifuse bitcells including a first MTJ antifuse bitcell and a second MTJ antifuse bitcell, wherein each MTJ antifuse bitcell of the plurality of MTJ antifuse bitcells includes:
- an MTJ having a first electrode and a second electrode and a magnetoresistive stack/structure disposed therebetween, wherein the MTJ is configured in only one of:
- (i) a programmed antifuse state or (ii) unprogrammed antifuse state, wherein if the MTJ is configured in the unprogrammed antifuse state, the MTJ is configurable in an unprogrammed low state and an unprogrammed high state, and
- a first select transistor electrically coupled to the first electrode of the MTJ of the associated MTJ antifuse bitcell, wherein the first select transistor includes a gate;
- a first reference resistor;
- a second select transistor, electrically coupled to the first reference resistor, wherein the second select transistor includes a gate;
- a plurality of electrical conductors, including first and second electrical conductors, wherein the first MTJ antifuse bitcell is coupled to the first electrical conductor and the first reference resistor is coupled to the second electrical conductor;
- a sense amplifier having a first input electrically coupled to the first electrical conductor and a second input electrically coupled to the second electrical conductor;
- and
- wherein, in a first operation, (i) the first select transistor of the first MTJ antifuse bitcell is responsively enabled, via a voltage applied to the gate thereof, to electrically connect the MTJ of the first MTJ antifuse bitcell to the sense amplifier via the first electrical conductor and (ii) the second select transistor is responsively enabled, via a voltage applied to the gate thereof, to electrically connect the reference resistor to the sense amplifier via the second electrical conductor, and wherein the sense amplifier is configured to sense whether the MTJ of the first MTJ antifuse bitcell is in the programmed antifuse state or the unprogrammed antifuse state.
7 more elements
A method of determining the antifuse state of a first magnetoresistive tunnel junction (MTJ) antifuse bitcell of an antifuse circuit, wherein the first MTJ antifuse bitcell is one of a plurality of MTJ antifuse bitcells of the antifuse circuit, wherein each MTJ antifuse bitcell includes:
- (a) an MTJ having a plurality of electrodes and a magnetoresistive stack/structure disposed therebetween, wherein the MTJ is configured in only one of (i) a programmed antifuse state which corresponds to the MTJ having a resistance in a first resistance range or (ii) an unprogrammed antifuse state, and wherein if the MTJ is configured in the unprogrammed antifuse state, the MTJ is configurable in an unprogrammed low state which corresponds to the MTJ having a resistance in a second resistance range, wherein the resistances of the second resistance range are greater than the resistances of the first resistance range, and an unprogrammed high state which corresponds to the MTJ having a resistance in a third resistance range wherein a majority of the resistances of the third resistance range are greater than all of the resistances of the first and second resistance ranges, the method of reading the first MTJ antifuse bitcell of the antifuse circuit comprises:
- performing a write operation to write the unprogrammed high state to the MTJ of the first MTJ antifuse bitcell;
- and
- immediately after performing the writing operation to write the unprogrammed high state to the MTJ of the first MTJ antifuse bitcell, performing a read operation of the first MTJ antifuse bitcell, including sensing a resistance of the MTJ of the first MTJ antifuse bitcell, wherein:
- (i) if the resistance of the MTJ of the first MTJ antifuse bitcell is below a resistance of a lower limit of the third resistance range, the MTJ of the first MTJ antifuse bitcell is in the programmed antifuse state, and
- (ii) if the resistance of the MTJ of the first MTJ antifuse bitcell is greater than the lower limit of the third resistance range, the MTJ of the first MTJ antifuse bitcell is in the unprogrammed antifuse state.
3 more elements
An antifuse circuit, comprising:
- a plurality of magnetoresistive tunnel junction (MTJ) antifuse bitcells including a first MTJ antifuse bitcell and a second MTJ antifuse bitcell, wherein each MTJ antifuse bitcell of the plurality of MTJ antifuse bitcells includes:
- an MTJ having a first electrode and a second electrode and a magnetoresistive stack/structure disposed therebetween, wherein the MTJ is configured in only one of:
- (i) a programmed antifuse state or (ii) unprogrammed antifuse state, wherein the unprogrammed antifuse state includes an unprogrammed low state and an unprogrammed high state, and
- a first PMOS transistor coupled to the first electrode of the MTJ of the associated MTJ antifuse bitcell, wherein the first PMOS transistor includes a gate;
- a first reference resistor;
- a second reference resistor;
- a plurality of electrical conductors, including:
- a first electrical conductor coupled to the first MTJ antifuse bitcell and second reference resistor, and
- a second electrical conductor coupled to the second MTJ antifuse bitcell and the first reference resistor;
- a sense amplifier having a first input coupled to the first electrical conductor and a second input coupled to the second electrical conductor;
- and
- wherein, in a first operation, (i) the first PMOS transistor of the first MTJ antifuse bitcell is responsively enabled, via a voltage applied to the gate thereof, to electrically connect the MTJ of the first MTJ antifuse bitcell to the sense amplifier via the first electrical conductor, and wherein the sense amplifier is configured to sense whether the MTJ of the first MTJ antifuse bitcell is in the programmed antifuse state or the unprogrammed antifuse state based on an amount of resistance of the MTJ of the first MTJ antifuse bitcell and an amount of resistance of the first reference resistor.
9 more elements
Dependencies are inferred from the claim text.