# US 12,141,511 B2 · Automated circuit generation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,141,511 B2 - Document ID: US12141511B2 - Status: Granted - Kind: B2 - Application number: 18/314,012 - Filed: 2023-05-08 - Published: 2023-08-31 - Granted: 2024-11-12 - Earliest claimed: 2019-05-30 - Assignees: Celera Corporation - Applicants: Celera, Inc. - Inventors: Calum MacRae; John Mason; Karen Mason - Web page: https://patentgrep.com/patent/US12141511B2 ## CPC - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F 30/31: Design entry, e.g. editors specifically adapted for circuit design - G06F 30/347: Physical level, e.g. placement or routing - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F 30/38: Circuit design at the mixed level of analogue and digital signals - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 30/373: Design optimisation - G06F 2111/12: Symbolic schematics - G06F 2111/20: Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Some embodiments of the present disclosure include techniques for generating a capacitor comprising receiving a total capacitance for a capacitor to be generated, determining a number N of unit capacitors having a unit capacitance to be combined to form the total capacitance, generating a transistor level schematic comprising N unit capacitor schematics having the unit capacitance, wherein the N unit capacitor schematics are configured to produce the total capacitance, and generating a layout comprising N capacitor layout elements configured to produce said capacitor. ## Claims ### Claim 1 A computer-implemented method of generating a capacitor comprising: receiving a total capacitance for a capacitor to be generated; determining a number N of unit capacitors having a unit capacitance to be combined to form the total capacitance; generating a transistor level schematic comprising N unit capacitor schematics having the unit capacitance, wherein the N unit capacitor schematics are configured to produce the total capacitance; and generating a layout comprising N capacitor layout elements configured to produce said capacitor. ### Claim 2 (depends on 1) The method of claim 1, wherein the total capacitance is produced based on information specifying a circuit to be generated. ### Claim 3 (depends on 2) The method of claim 2, wherein the total capacitance is produced based on a predefined circuit model for the circuit to be generated. ### Claim 4 (depends on 1) The method of claim 1, wherein the total capacitance is received as a parameter corresponding to a capacitor functional circuit component. ### Claim 5 (depends on 1) The method of claim 1, further comprising comparing the total capacitance to a predefined maximum capacitance, wherein the N unit capacitor schematics are configured in parallel when the total capacitance is greater than the predefined maximum capacitance. ### Claim 6 (depends on 1) The method of claim 1, further comprising comparing the total capacitance to a predefined minimum capacitance, wherein the N unit capacitor schematics are configured in series when the total capacitance is less than the predefined minimum capacitance. ### Claim 7 (depends on 1) The method of claim 1, wherein the number N of unit capacitors is an integer greater than or equal to one (1). ### Claim 8 (depends on 1) The method of claim 1, further comprising: configuring a first length corresponding to a first dimension of the N unit capacitors to be less than or equal to a predefined maximum length along the first dimension; and determining a second length corresponding to a second dimension of the N unit capacitors based on at least the unit capacitance and the first length. ### Claim 9 (depends on 8) The method of claim 8, wherein the first length is set to the predefined maximum length along the first dimension. ### Claim 10 (depends on 8) The method of claim 8, wherein the first length and second length are configured to produce a predefined aspect ratio of the first length and the second length. ### Claim 11 (depends on 8) The method of claim 8, the method further comprising iteratively adjusting the first length to produce an adjusted second length until an aspect ratio of the first length and the second length meet a predetermined aspect ratio. ### Claim 12 (depends on 11) The method of claim 11, wherein the first length is initially the predefined maximum length and the first length is iteratively reduced. ### Claim 13 (depends on 8) The method of claim 8 further comprising generating a circuit specification comprising N components corresponding to the N unit capacitors. ### Claim 14 (depends on 13) The method of claim 13, wherein the circuit specification is a netlist. ### Claim 15 (depends on 13) The method of claim 13, wherein one or more attributes of the N unit capacitors are encoded in the circuit specification. ### Claim 16 (depends on 8) The method of claim 8, wherein the N unit capacitor schematics have a first attribute set to the first length and a second attribute set to the second length. ### Claim 17 (depends on 8) The method of claim 8, wherein the N capacitor layout elements comprise polygons having a first dimension equal to the first length and a second dimension equal to the second length. ### Claim 18 (depends on 1) The method of claim 1, said generating a transistor level schematic comprising: generating N schematic symbols; and automatically inserting into each of the N schematic symbols a capacitor symbol component. ### Claim 19 A computer system for generating a capacitor comprising: one or more processors; and a non-transitory computer-readable storage medium having stored thereon computer executable instructions, which when executed by the computer system, cause the computer system to perform a method comprising: receiving a total capacitance for a capacitor to be generated; determining a number N of unit capacitors having a unit capacitance to be combined to form the total capacitance; generating a transistor level schematic comprising N unit capacitor schematics having the unit capacitance, wherein the N unit capacitor schematics are configured to produce the total capacitance; and generating a layout comprising N capacitor layout elements configured to produce said capacitor. ### Claim 20 (depends on 19) The computer system of claim 19, wherein the total capacitance is produced based on parameters specifying a circuit to be generated. ### Claim 21 (depends on 19) The computer system of claim 19, wherein the number N of unit capacitors is an integer greater than or equal to one (1). ### Claim 22 (depends on 19) The computer system of claim 19, wherein the method further comprising: configuring a first length corresponding to a first dimension of the N unit capacitors to be less than or equal to a predefined maximum length along the first dimension; and determining a second length corresponding to a second dimension of the N unit capacitors based on at least the unit capacitance and the first length. ### Claim 23 (depends on 22) The computer system of claim 22, wherein the method further comprising iteratively adjusting the first length to produce an adjusted second length until an aspect ratio of the first length and the second length meet a predetermined aspect ratio. ### Claim 24 (depends on 19) The computer system of claim 19, wherein the method further comprising generating a netlist comprising N components corresponding to the N unit capacitors and generating a transistor level schematic comprising the N unit capacitors using the netlist. ### Claim 25 A non-transitory computer-readable storage medium having stored thereon computer executable instructions, which when executed by a computer system, cause the computer system to: receive a total capacitance for a capacitor to be generated; determine a number N of unit capacitors having a unit capacitance to be combined to form the total capacitance; generate a transistor level schematic comprising N unit capacitor schematics having the unit capacitance, wherein the N unit capacitor schematics are configured to produce the total capacitance; and generate a layout comprising N capacitor layout elements configured to produce said capacitor. ### Claim 26 (depends on 25) The non-transitory computer-readable storage medium of claim 25, wherein the total capacitance is produced based on parameters specifying a circuit to be generated. ### Claim 27 (depends on 25) The non-transitory computer-readable storage medium of claim 25, wherein the number N of unit capacitors is an integer greater than or equal to one (1). ### Claim 28 (depends on 25) The non-transitory computer-readable storage medium of claim 25, wherein the instructions, which when executed by the computer system, further cause the computer system to perform: further comprising: configuring a first length corresponding to a first dimension of the N unit capacitors to be less than or equal to a predefined maximum length along the first dimension; and determining a second length corresponding to a second dimension of the N unit capacitors based on at least the unit capacitance and the first length. ### Claim 29 (depends on 28) The non-transitory computer-readable storage medium of claim 28, wherein the instructions, which when executed by the computer system, further cause the computer system to perform iteratively adjusting the first length to produce an adjusted second length until an aspect ratio of the first length and the second length meet a predetermined aspect ratio. ### Claim 30 (depends on 25) The non-transitory computer-readable storage medium of claim 25, wherein the instructions, which when executed by the computer system, further cause the computer system to perform generating a netlist comprising N components corresponding to the N unit capacitors and generating a transistor level schematic comprising the N unit capacitors using the netlist.