Scan testing in a processor

A processor comprising:

• a plurality of processing units;
• an exchange comprising a plurality of exchange paths connected to respective ones of the plurality of processing units and configured to output data to a connected exchange path for transmitting data between the processing units, wherein each of the plurality of processing units is configured to execute test software to perform an exchange path functional test to identify a first defective exchange path of the plurality of exchange paths;
• and
• repair logic connected to the processing units and comprising switching circuitry configurable by a repair code configured to switch out a first processing unit of the plurality of processing units, responsive to the first processing unit being connected to a first defective exchange path of the plurality of exchange paths, and further configured to switch in a first repair processing unit connected to a first non-defective exchange path for functional operation of the processor;
• and
• an exchange scan chain comprising selectable scan chain components and switch circuitry configured to remove scan chain components connected to the first defective exchange path, wherein the exchange scan chain is configured to enable scan testing of the plurality of exchange paths excluding any of the exchange paths identified as defective.

A system for effecting a repair in a processor having an exchange with a plurality of exchange paths for transmitting data between a plurality of processing units of the processor, the system comprising:

• a repair engine configured to detect a first defective exchange path of the plurality of exchange paths;
• repair logic connected to the processing units and configured to switch a first processing unit of the plurality of processing units responsive to the first processing unit being connected to the first defective exchange path and further configured to switch the first processing unit out of functional operation of the processor and switch in a first repair processing unit connected to a first non-defective exchange path for functional operation of the processor;
• and
• an exchange scan chain comprising selectable scan chain components and switch circuitry configured to remove scan chain components connected to the first defective exchange path, wherein the exchange scan chain is configured to enable scan testing of the plurality of exchange paths excluding any of the exchange paths identified as defective.