Pulse elimination circuit, voltage detection circuit and detecting method

A pulse elimination circuit comprising:

• a clock generation circuit, configured to receive a logic signal and a first input signal and generate a clock signal based on the logic signal and the first input signal;
• a counter, coupled with the clock generation circuit and configured to receive the clock signal and count a number of cycles of the clock signal to generate a second input signal;
• a signal output circuit, coupled to the counter and configured to supply the first input signal to the clock generation circuit and to generate a pulse elimination signal based on the second input signal,
• wherein the clock generation circuit comprises:
• a first AND gate circuit, wherein one input terminal of the first AND gate circuit is configured to receive the logic signal, and another input terminal of the first AND gate circuit is configured to receive the first input signal;
• an oscillator, which has an enable terminal coupled with an output terminal of the first AND gate circuit;
• a second AND gate circuit, which has one input terminal configured to receive the first input signal, another input terminal coupled to a clock pulse output terminal of the oscillator, and an output terminal coupled to the counter and configured to output the clock signal to the counter.