Clock synthesizer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorWei Shuo Lin
Life of this patent
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Abstract
A clock synthesizer is provided. The Clock synthesizer includes a a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer is configured to store the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit is configured to receive the clock signal from the clock buffer, adjust a duty cycle of the clock signal to substantially equal to 50%, perform phase interpolation on the clock signal, and provide the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.
Claims20
A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit comprising:
- a phase interpolator operative to receive a clock signal having a first phase value and provide an output clock signal having a second phase value;
- a first Direct Current (DC) sampler operative to determine an average DC voltage value of inverted output clock signal;
- a second DC sampler operative to determine an average DC voltage value of the output clock signal;
- an error amplifier connected to the first DC sampler and the second DC sampler, wherein the error amplifier is operative to determine a difference between the average DC voltage value of the inverted output clock signal and the average DC voltage of the clock signal;
- and
- a voltage/current alternator connected to an output of the error amplifier, wherein the voltage/current alternator is operative to adjust a duty cycle of the output clock signal based on the difference between the average DC voltage value of the inverted output clock signal and the average DC voltage of the output clock signal.
A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit comprising:
- a phase interpolator operative to receive a clock signal having a first phase value and provide an output clock signal having a second phase value;
- a first Direct Current (DC) sampler operative to determine an average DC voltage value of inverted output clock signal;
- a second DC sampler operative to determine an average DC voltage value of the output clock signal;
- and
- a comparator connected to the first DC sampler and the second DC sampler, wherein the comparator is operative to:
- compare the average DC voltage value of the inverted clock signal and the average DC voltage value of the clock signal,
- provide a first value as an output when the average DC voltage value of the inverted clock signal is greater than the average DC voltage value of the clock signal, and
- provide a second value as the output when the average DC voltage value of the inverted clock signal is less than the average DC voltage of the clock signal.
A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit comprising:
- a phase interpolator operative to receive a first clock signal having a first phase value and provide a clock signal having a first phase value and provide the clock signal having a second phase value;
- a first Direct Current (DC) sampler operative to determine an average DC voltage value of the clock signal having the first phase value;
- a second DC sampler operative to determine an average DC voltage value of the clock signal having the second phase value;
- an error amplifier connected to the first DC sampler and the second DC sampler, wherein the error amplifier is operative to determine a difference between the average DC voltage value of the clock signal having the first phase value and the average DC voltage of the clock signal having the second phase value;
- and
- a voltage/current alternator connected to an output of the error amplifier, wherein the voltage/current alternator is operative to adjust a duty cycle of the clock signal based on the difference between the average DC voltage value of the clock signal having the first phase value and the average DC voltage of the clock signal having the second phase value.
Dependencies are inferred from the claim text.