Systems and methods for low latency modular multiplication

A method comprising:

• determining, via multiplier circuitry of an integrated circuit device, a plurality of columns of subproducts by multiplying a plurality of values, wherein the plurality of columns of subproducts comprises a plurality of subproducts and each column of the plurality of columns comprises one or more subproducts of the plurality of subproducts;
• and
• determining, via adder circuitry of the integrated circuit device, a plurality of sums, wherein each sum of the plurality of sums is a sum of one column of the plurality of columns, wherein determining the plurality of sums comprises:
• receiving, via a first portion of the adder circuitry associated with a first column of the plurality of columns, a first value associated with the first column, a second value associated with the first column, and a third value associated with a second column of the plurality of columns that differs from the first column, wherein the third value is a carry-out value generated by a second portion of the adder circuitry associated with the second column of the plurality of columns;
• determining, via the first portion of the adder circuitry, a sum of a first portion of the first value, a second portion of the second value, and the third value;
• and
• generating, via the integrated circuit device, a plurality of modulus values from a portion of the plurality of sums, wherein the plurality of modulus values are added in an order based on latencies associated with determining the plurality of sums.

A programmable logic device configurable to be programmed to perform modular multiplication, wherein, when programmed, the programmable logic device comprises:

• multiplier circuitry configured to determine a plurality of columns of subproducts by multiplying a plurality of values, wherein the plurality of columns of subproducts comprises a plurality of subproducts and each column of the plurality of columns comprises one or more subproducts of the plurality of subproducts;
• and
• adder circuitry at least partially implemented in programmable logic of the programmable logic device, wherein the adder circuitry is configured to determine a plurality of sums, wherein each sum of the plurality of sums is a sum of one column of the plurality of columns, wherein a first portion of the adder circuitry associated with a first column of the plurality of columns is configured to receive a first value associated with the first column, a second value associated with the first column, and a third value associated with a second column of the plurality of columns that differs from the first column, wherein the third value is a carry-out value generated by a second portion of the adder circuitry associated with the second column of the plurality of columns, and wherein the first portion of the adder circuitry comprises:
• ternary adder circuitry configured to add a first portion of the first value, a second portion of the second value, and the third value, wherein the first portion of the first value, the second portion of the second value, and the third value each include a first number of bits;
• compressor circuitry communicatively coupled to the ternary adder circuitry, wherein the compressor circuitry is configured to receive a first remaining portion of the first value and a second remaining portion of the second value, wherein the first remaining portion of the first value and the second remaining portion of the second value each include a second number of bits, wherein the second number of bits is greater than the first number of bits;
• and
• binary adder circuitry communicatively coupled to the compressor circuitry, wherein the binary adder circuitry is configured to output a sum of the first remaining portion of the first value and the second remaining portion of the second value.