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US 12,135,351 B2Granted
DFT architecture for analog circuits
AssigneeSTMicroelectronics S.r.l.
InventorFilippo Colombo
Life of this patent
Estimating the term…
Abstract
An integrated circuit (IC) includes: a first functional analog pin or pad; a first analog test bus coupled to the first functional analog pin or pad; first and second analog circuits coupled to the first analog test bus; and a test controller configured to: when the IC is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus so that the input or output of the first analog circuit is accessible by the first functional analog pin or pad, and keep disconnected an input or output of the second analog circuit from the first analog test bus, and when the IC is in a test mode, selectively connect the input or output of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus.
Claims23
An integrated circuit comprising:
- a first functional analog pin or pad;
- a first analog test bus coupled to the first functional analog pin or pad;
- a plurality of analog-to-digital converters (ADCs) having first inputs coupled to the first analog test bus;
- a plurality of digital-to-analog converters (DACs) having outputs coupled to the first analog test bus;
- a plurality of comparators having first inputs coupled to the first analog test bus:
- a first analog circuit coupled to the first analog test bus, the first analog circuit comprising a DAC of the plurality of DACs, an ADC of the plurality of ADCs, or a comparator of the plurality of comparators;
- a second analog circuit coupled to the first analog test bus;
- and
- a test controller configured to:
- when the integrated circuit is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus so that the input or output of the first analog circuit is accessible by the first functional analog pin or pad, and keep disconnected an input or output of the second analog circuit from the first analog test bus,
- when the integrated circuit is in a test mode, selectively connect the input or output of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus connect the respective first inputs of each of the plurality of comparators to the first analog test bus,
- provide an analog signal to the first analog test bus with the output of a first DAC in response to the first inputs of the plurality of ADCs and the first inputs of the plurality of comparators being connected to the first analog test bus, and
- determine whether a comparator has a fault based on respective outputs of the plurality of comparators.
10 more elements
An integrated circuit comprising:
- first and second functional analog pins or pads;
- first and second analog test buses respectively coupled to the first and second functional analog pins or pads;
- a first digital-to-analog converter (DAC) having an output coupled to the first analog test bus;
- a second DAC having an output coupled to the second analog test bus;
- a differential analog-to-digital converter (ADC) having a first input coupled to the first analog test bus and a second input coupled to the second analog test bus;
- and
- a test controller configured to:
- when the integrated circuit is in a functional operating mode, connect the output of the first DAC to the first analog test bus so that the output of the first DAC is accessible by the first functional analog pin or pad, connect the output of the second DAC to the second analog test bus so that the output of the second DAC is accessible by the second functional analog pin or pad, and keep disconnected the first and second inputs of the differential ADC from the first and second analog test buses, respectively, and
- when the integrated circuit is in a test mode, connect the first and second inputs of the differential ADC to the first and second analog test buses, respectively, provide first and second analog signals to the first and second analog test buses using the first and second DACs, respectively, and determine whether the first DAC, the second DAC, or the differential ADC has a fault based on an output of the differential ADC.
6 more elements
A method comprising:
- when an integrated circuit is in a non-test mode,
- connect an input or output of a first analog circuit to a first analog test bus that is coupled to a first functional analog pin or pad so that the input or output of the first analog
- circuit is accessible by the first functional analog pin or pad, and
- keep disconnected an input or output of a second analog circuit from the first analog test bus;
- when the integrated circuit is in a test mode, selectively connect the input or output of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus;
- when the integrated circuit is in the functional operating mode, connect an input or output of a third analog circuit to a second analog test bus so that the input or output of the third analog circuit is accessible by a second functional analog pin or pad, and keep disconnected an input or output of a fourth analog circuit from the second analog test bus:
- and when the integrated circuit is in the test mode, test the third analog circuit using the second analog test bus, connect the input or output of the fourth analog circuit to the second analog test bus, and test the fourth analog circuit using the first analog test bus.
4 more elements
Dependencies are inferred from the claim text.