Caching of logical-to-physical mapping information in a memory sub-system

A method comprising:

• receiving, by a primary flash translation layer (FTL) of a memory sub-system controller, a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device;
• providing, by the primary FTL, a look-up request to a secondary FTL of the memory sub-system controller based on the request, the look-up request specifying the logical address;
• accessing, by the secondary FTL, from a volatile memory component, a logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device;
• determining an entry in the L2P table that corresponds to the logical address points to an entry in a read cache table,
• identifying, by the secondary FTL, a physical address that corresponds to the logical address specified by the request based on a chunk in a read cache corresponding to a chunk address determined based on an entry number of the entry in the read cache table, the physical address corresponding to a physical location in the first portion of memory device;
• providing, by the secondary FTL, the physical address to the primary FTL responsive to the look-up request;
• and
• performing, by the primary FTL, the host-initiated operation at the physical location within the first portion of the memory device corresponding the physical address that corresponds to the logical address specified by the request.

A computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising:

• receiving, by a primary flash translation layer (FTL) of the processing device, a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device;
• providing, by the primary FTL, a look-up request to a secondary FTL of the processing device based on the request, the look-up request specifying the logical address;
• accessing, by the secondary FTL, from a volatile memory component, a logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device;
• determining, by the secondary FTL, an entry in the L2P table that corresponds to the logical address points to an entry in a read cache table;
• identifying, by the secondary FTL, based on a chunk in a read cache corresponding to a chunk address determined based an entry number of the entry in the read cache table, a physical address that corresponds to the logical address specified by the request, the physical address corresponding to a physical location in the first portion of memory device;
• providing, by the secondary FTL, the physical address to the primary FTL responsive to the look-up request;
• and
• performing, by the primary FTL, the host-initiated operation at the physical location within the first portion of the memory device corresponding the physical address that corresponds to the logical address specified by the request.