Delay time detection circuit, stamping information generation device, and delay time detection method

A delay time detection circuit that detects a delay time of an input clock signal having a first period with respect to a system clock signal by use of the system clock signal corresponding to a main scale and having the first period, and a sub scale clock signal corresponding to a sub scale and having a second period differing from the first period, the delay time detection circuit comprising:

• a clock generation unit configured to generate a sub scale clock signal, based on the system clock signal;
• a count unit configured to generate a count signal while sequentially and repeatedly incrementing a preset count number, based on the sub scale clock signal;
• a sub scale signal generation unit configured to receive the count signal, and to generate sub scale signals, equal in number to the count number, that each have, at a rate of once in the count number, a rectangular wave for a duration being associated with the second period and that are shifted in timing relative to one another according to the second period;
• a delay time calculation unit configured to receive the input clock signal, and to calculate a delay time within a range of the first period of the input clock signal with respect to the system clock signal, based on one of the sub scale signals having a timing coinciding with the input clock signal among a plurality of the sub scale signals;
• a count number calculation unit configured to receive a value of the second period as a setting value, and to determine the count number, based on the received setting value and the first period,
• wherein the delay time calculation unit processes, as a timing coinciding with the input clock signal, either
• a case where two or more rising edges of the input clock signal are included within a duration being associated with the second period of the rectangular wave, or
• a case where two or more falling edges of the input clock signal are included within a duration being associated with the second period of the rectangular wave,
• wherein the sub scale clock signal generated by the clock generation unit has the second period being longer than the first period and shorter than a period twice the first period,
• wherein the count number calculation unit sets, as the count number, a minimum value of a first value when a remainder of a division becomes zero,
• wherein the division is defined by dividing a second value by a third value,
• wherein the first value is a quotient of the division,
• wherein the third value is a difference between the setting value and the first period, and
• wherein the second value is a multiplicative period of a value of the first period by any natural number becomes zero.