Shuffler-free ADC error compensation

An apparatus for error compensation, the apparatus comprising:

• an analog-to-digital converter circuit, ADC, configured and arranged to convert an analog signal being an input signal into a digital signal being a digital output;
• at least two digital-to-analog converter circuits, DACs, each being configured and arranged to convert a portion of the digital signal into a further analog signal;
• and
• a compensation circuit configured and arranged to correct the digital output of the ADC by:
• for each DAC of the at least two DACs, generating a feedback signal indicative of an incompatibility between an analog output of the DAC, as converted to a digital signal by the ADC, and digital inputs provided to the DAC, wherein the feedback signal is based on a DAC error estimate that converges to a suitable level;
• for each DAC of the at least two DACs, applying a respective gain to the digital input to the DAC based on the feedback signal for the DAC, therein providing a modified digital signal;
• and
• generating the corrected output based on a combination of the digital signal output from the ADC and the modified digital signals provided by the at least two DACs;
• wherein generating the feedback signal includes subtracting an averaged value corresponding to the digital inputs provided to all of the at least two DACS;
• and
• wherein the digital inputs provided to the at least two DACs are non-randomized.