Clock enabler circuit
AssigneeSony Semiconductor Solutions Corporation
InventorYoshinori Tanaka
Life of this patent
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Abstract
An unnecessary circuit operation in a clock enabler circuit accompanying toggling of a clock signal is suppressed. A state holding unit performs a holding operation of a state as to whether or not to output an output clock signal according to an internal clock signal. A clock signal output unit controls output of the output clock signal according to the state held in the state holding unit. A control unit supplies, to the state holding unit, the internal clock signal and a value of the state that are necessary for the holding operation in the state holding unit on a basis of a clock signal and a clock enable signal from an outside.
Claims10
A clock enabler circuit, comprising:
- a state holding unit configured to perform, based on an internal clock signal, a holding operation of a state, wherein the state indicates whether to output an output clock signal;
- a clock signal output unit configured to control the output of the output clock signal based on the state held in the state holding unit;
- and
- a control unit configured to:
- receive a clock signal and a clock enable signal from an outside of the control unit;
- and
- supply, to the state holding unit, the internal clock signal and a value of the state that are for the holding operation, wherein
- the supply is based on the clock signal and the clock enable signal, and
- the state holding unit includes a delay unit configured to delay a timing at which the value of the state is supplied to the state holding unit.
Dependencies are inferred from the claim text.