Vertically stacked diode-trigger silicon controlled rectifier

A structure comprising:

• a silicon controlled rectifier on a trap rich region of a silicon substrate;
• and
• at least one diode vertically integrated with the silicon controlled rectifier, the at least one diode includes a P+ region and N+ region in polysilicon and isolated from an underlying semiconductor substrate by being in direct contact with a gate dielectric material, the P+ region and N+ region being separated by a p-type diffusion region which is also in direct contact with the gate dielectric material,
• wherein the underlying semiconductor substrate comprises a p-well under the gate dielectric material and an n-well adjacent to the p-well
• the silicon controlled rectifier comprises an anode over the n-well and a cathode over the p-well;
• the silicon rectifier comprises a P+ diffusion region connected to the anode, an N+ diffusion region connected to the P+ region of the at least one diode, a second N+ diffusion region connected to the N+ region of the at least one diode, and a second P+ diffusion region connected to the cathode and the N+ diffusion region;
• and
• the least one diode comprising a gate structure comprising the P+ region and the N+ region separated by the p-type diffusion region.

A method comprising:

• forming a silicon controlled rectifier on a trap rich region of a semiconductor substrate;
• and
• forming at least one diode sitting on a gate dielectric material and comprising a first diffusion region of a first dopant type, a second diffusion region of a second dopant type and a third diffusion of the first dopant type separating the first diffusion region from the second diffusion region, over the trap rich region of the semiconductor substrate, wherein
• the at least one diode is provided in a polysilicon material comprising a P+ region and an N+ region, separated by and directly contacting a p-type diffusion region, each of which sit on and directly contact the gate dielectric material,
• the silicon rectifier comprises a P+ diffusion region connected to an anode, an N+ diffusion region connected to the P+ region of the at least one diode, a second N+ diffusion region connected to the N+ region of the at least one diode and a second P+ diffusion region connected to a cathode and the N+ diffusion region of the silicon rectifier, and
• the at least one diode is isolated from the semiconductor substrate by the gate dielectric material, the P+ diffusion region of the silicon rectifier connected to the anode and the N+ diffusion region of the silicon rectifier connected to the P+ region of the at least one diode are provided in an n-well, and the second N+ diffusion region of the of the silicon rectifier connected to the N+ region of the at least one diode and the second P+ diffusion region of the silicon rectifier connected to the cathode are provided in a p-well, and the p-well and the n-well directly contact the trap rich region.