Memory device and semiconductor device including the same

A memory device comprising:

• a plurality of memory chips including a first memory chip and a second memory chip, the first memory chip including a first plurality of memory cell rows and the second memory chip including a second plurality of memory cell rows,
• wherein
• the first memory chip is configured to perform a refresh operation on a first memory cell row of the first plurality of memory cell rows corresponding to a first refresh row address in response to a refresh command, and
• the second memory chip is configured to perform the refresh operation on a second memory cell row of the second plurality of memory cell rows corresponding to a second refresh row address, which is different from the first refresh row address, in response to the refresh command, while the first memory chip is performing the refresh operation on the first memory cell row.

A semiconductor device comprising:

• a memory controller configured to provide a mode register set command and a refresh command;
• and
• a memory device including a plurality of memory chips that are stacked, each of the memory chips including a plurality of memory cell rows and a refresh counter configured to generate a target row address for refreshing a memory cell row of the plurality of memory cell rows in response to the refresh command,
• wherein
• the mode register set command includes a setting value for converting the target row address into a refresh row address by one of inverting and not inverting the target row address, during a refresh operation performed in response to the refresh command, and
• each of the memory chips is configured to store the setting value in a mode register in response to the mode register set command and perform the refresh operation on a memory cell row corresponding to one of the target row address and the inverted target row address in response to the refresh command, and
• wherein the inverted target row address is obtained by inverting the target row address in a refresh address generator of the memory device based on the setting value.