US 12,125,124 B1 · Matrix transpose hardware acceleration

Abstract

In one example, an apparatus comprises: a buffer memory; and a memory access circuit configured to: fetch, from a first memory, a set of first groups of data elements of a first matrix, each first group of data elements being stored at consecutive memory addresses at the first memory; based on a first configuration, store the set of first groups of data elements at consecutive memory addresses or at non-consecutive memory addresses at the buffer memory; based on a second configuration that defines a memory address offset, fetch a set of second groups of the data elements from the buffer memory, each second group of the data elements being stored at consecutive memory addresses of the buffer memory, each second group being separated by the memory address offset in the buffer memory; and store each fetched second group at consecutive addresses of a destination memory to form a second matrix.

Claims20

Dependent claims

A memory access circuit configured to perform a transpose operation, comprising:

an x-striding circuit configured to:
fetch data elements of a first matrix from a source memory, the data elements comprising a set of first groups of the data elements;
and
store the set of first groups of the data elements at a buffer memory based on a first transpose configuration, wherein the first transpose configuration is indicated by a command that is received by the memory access circuit;
and
a y-striding circuit configured to:
fetch a set of second groups of the data elements from the buffer memory based on a second transpose configuration, wherein the second transpose configuration is indicated by the command that is received by the memory access circuit;
and
store the set of second groups of the data elements at a destination memory to form a second matrix, the second matrix being a transposed version of the first matrix;
wherein the buffer memory is separate from the source memory and the destination memory, and wherein, during the transpose operation, the y-striding circuit is configured to read from but not write to the buffer memory.

7 more elements

Dependencies are inferred from the claim text.

Matrix transpose hardware acceleration

Life of this patent

Matrix transpose hardware acceleration

Life of this patent

Abstract

Claims20