System-on-chip comprising a non-volatile memory

A non-transitory computer-readable medium having contents which cause a processing system to perform a method, the method comprising:

• storing logical memory bank configuration information in one or more configuration registers of a memory interface coupled to a memory of a system-on-a-chip, the memory including one or more physical banks divided into a plurality of sectors, each sector having a size equal to a smallest erasable size of the memory, the stored logical memory bank configuration information assigning each sector of the one or more physical banks of the memory to a respective logical memory bank of a plurality of logical memory banks;
• and
• controlling access to the memory by a processor of the system-on-a-chip based on the logical memory bank configuration information stored in the one or more configuration registers, wherein,
• the memory interface defines the plurality of logical memory banks at different addresses, and
• the stored logical memory bank configuration information defines a first logical memory bank to store compiled code of an application and a second logical memory bank to store an updated version of the compiled code of the application, the first and second logical memory banks having an equal number of assigned memory sectors and being interchangeable.

A device, comprising:

• a host processor;
• and
• a system-on-a-chip coupled to the host processor, the system-on-a-chip having:
• one or more processing cores, which, in operation, generate memory access requests;
• a memory including one or more physical banks divided into a succession of sectors, each sector having a size equal to a smallest erasable size of the memory;
• and
• a memory interface coupled to the memory and to the one or more processing cores, the memory interface including one or more configuration registers, wherein the memory interface, in operation:
• in response to receiving memory configuration information, stores logical memory bank configuration information in the one or more configuration registers, the logical memory bank configuration information assigning each sector of the one or more physical banks of the memory to a respective logical memory bank of a plurality of logical memory banks;
• and
• in response to receiving a memory access request from the one or more processing cores, controls access to the memory based on the logical memory bank configuration information stored in the one or more configuration registers, wherein,
• the memory interface defines the plurality of logical memory banks at different addresses, and
• the stored logical memory bank configuration information defines a first logical memory bank to store compiled code of an application and a second logical memory bank to store an updated version of the compiled code of the application, the first and second logical memory banks having an equal number of assigned memory sectors and being interchangeable.