# US 12,120,962 B2 · Method for fabricating semiconductor device

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- Number: US 12,120,962 B2
- Document ID: US12120962B2
- Status: Granted
- Kind: B2
- Application number: 18/504,176
- Filed: 2023-11-08
- Published: 2024-03-07
- Granted: 2024-10-15
- Earliest claimed: 2021-01-25
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Tai-Cheng Hou; Fu-Yu Tsai; Bin-Siang Tsai; Da-Jun Lin; Chau-Chung Hou; Wei-Xin Gao
- Web page: https://patentgrep.com/patent/US12120962B2

## CPC

- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/01: Manufacture or treatment
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/80: Constructional details
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a magnetoresistive random access memory (MRAM) region and a logic region;
forming a magnetic tunneling junction (MTJ) on the MRAM region;
forming a top electrode on the MTJ;
performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ, wherein a top surface of the first IMD layer on the logic region is lower than a top surface of the first IMD layer on the MRAM region and higher than a top surface of the top electrode, and the top surface of the first IMD layer directly on top of the MTJ and the top surface of the first IMD layer adjacent to the MTJ on the MRAM region comprise a completely planar surface;
performing a planarizing process to planarizing the first IMD layer after performing the FCVD process, wherein a height difference between the first IMD layer on the logic region and the first IMD layer on the MRAM region before the planarizing process is less than 400 Angstroms; and
forming a second metal interconnection on the logic region after planarizing the first IMD layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a second IMD layer on the MRAM region and the logic region;
forming a first metal interconnection in the second IMD layer on the MRAM region;
forming the MTJ on the first metal interconnection;
forming the first IMD layer on the MRAM region and the logic region;
removing the first IMD layer on the logic region; and
forming the second metal interconnection on the logic region.

### Claim 3 (depends on 2)

The method of claim 2, wherein a top surface of the top electrode is lower than a top surface of the second metal interconnection.

### Claim 4 (depends on 2)

The method of claim 2, further comprising:
forming a stop layer on the first IMD layer;
forming a third IMD layer on the stop layer; and
forming a third metal interconnection on the MRAM region to connect to the top electrode and a fourth metal interconnection on the logic region to connect to the second metal interconnection.

### Claim 5 (depends on 1)

The method of claim 1, further comprising performing a chemical mechanical polishing (CMP) process for planarizing the first IMD layer.