# US 12,120,918 B2 · Display device

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- Number: US 12,120,918 B2
- Document ID: US12120918B2
- Status: Granted
- Kind: B2
- Application number: 17/619,790
- Filed: 2020-06-15
- Published: 2022-11-03
- Granted: 2024-10-15
- Earliest claimed: 2019-06-28
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Hidetomo Kobayashi; Takayuki Ikeda
- Web page: https://patentgrep.com/patent/US12120918B2

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09F 9/30: in which the desired character or characters are formed by combining individual elements (panels comprising a number of electrodes in a single cell controlling light arriving from an independent light source, e.g. electro-optical or magneto-optical cell, G02F1/00)
- G09G 3/3225: using an active matrix
- H05B 33/02: Details
- H05B 33/14: characterised by the chemical or physical composition or the arrangement of the electroluminescent material {, or by the simultaneous addition of the electroluminescent material in or onto the light source}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 84/0126: {the components including insulated gates, e.g. IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10K 59/1213: {the pixel elements being TFTs}
- G09G 2300/023: Display panel composed of stacked panels
- H10K 59/12: Active-matrix OLED [AMOLED] displays
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G09F: DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- H05B: ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A display device with less display unevenness is provided. The display device includes a first layer and a second layer over the first layer; the first layer includes first circuits arranged in m rows and n columns; the second layer includes pixel blocks arranged in the m rows and the n columns; the pixel blocks each comprise pixels arranged in a rows and b columns; the pixel block includes a first wiring and a second wiring electrically connected to the pixel; the first wiring and the second wiring included in the pixel block in the i-th row and the j-th column are each electrically connected to the first circuit in the i-th row and the j-th column; the first wiring has a function of supplying an input signal from the first circuit to the pixel; and the second wiring has a function of supplying an output signal from the pixel to the first circuit.

## Claims

### Claim 1

A display device comprising a first layer and a second layer over the first layer,
wherein the first layer comprises first circuits arranged in m rows and n columns (m and n are each an integer greater than or equal to 1 and a product of m and n is an integer greater than or equal to 2),
wherein the second layer comprises pixel blocks arranged in the m rows and the n columns,
wherein the pixel blocks each comprise pixels arranged in a rows and b columns (a and b are each an integer greater than or equal to 1),
wherein the pixel block comprises a first wiring and a second wiring electrically connected to the pixel,
wherein the first wiring and the second wiring included in the pixel block in an i-th row and a j-th column (i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n) are each electrically connected to the first circuit in the i-th row and the j-th column,
wherein the first wiring is configured to supply an input signal from the first circuit to the pixel,
wherein the second wiring is configured to supply an output signal from the pixel to the first circuit,
wherein each of the first circuits comprises a correction data generation circuit, a logic circuit, and a source driver circuit,
wherein the correction data generation circuit is configured to convert the output signal into correction data,
wherein the logic circuit is configured to correct a video signal input to the first circuit on the basis of the correction data and generating the corrected video signal, and
wherein the source driver circuit is configured to convert the corrected video signal into the input signal.

### Claim 2 (depends on 1)

The display device according to claim 1,
wherein the pixel block in the i-th row and the j-th column has a region overlapping with the first circuit in the i-th row and the j-th column.

### Claim 3 (depends on 1)

The display device according to claim 1,
wherein the pixel block in a p-th row and a q-th column (p is an integer different from i and is greater than or equal to 1 and less than or equal to m, and q is an integer different from j and is greater than or equal to 1 and less than or equal to n) does not overlap with the first circuit in the p-th row and the q-th column.

### Claim 4 (depends on 1)

The display device according to claim 1,
wherein the second layer further comprises m second circuits arranged in a column direction,
wherein the pixel block comprises a third wiring electrically connected to a plurality of pixels arranged in a row direction, and
wherein the third wiring included in the pixel block in the i-th row is electrically connected to an i-th second circuit.

### Claim 5 (depends on 1)

The display device according to claim 1,
wherein the first layer further comprises m second circuits arranged in a column direction,
wherein the pixel block comprises a third wiring electrically connected to a plurality of pixels arranged in a row direction, and
wherein the third wiring included in the pixel block in the i-th row is electrically connected to an i-th second circuit.

### Claim 6 (depends on 5)

The display device according to claim 5,
wherein the pixel block in the i-th row and the j-th column comprises a region overlapping with at least one of the second circuits.

### Claim 7 (depends on 1)

The display device according to claim 1,
wherein the correction data generation circuit comprises a memory circuit,
wherein the first layer comprises a first circuit layer and a second circuit layer over the first circuit layer,
wherein the first circuit layer comprises the logic circuit,
wherein the logic circuit comprises a transistor comprising silicon in a channel formation region,
wherein the second circuit layer comprises the memory circuit,
wherein the memory circuit comprises a transistor comprising a metal oxide in a channel formation region, and
wherein the metal oxide comprises In, an element M (M is any one or more of Al, Ga, Y, and Sn), and Zn.

### Claim 8 (depends on 1)

The display device according to claim 1,
wherein the pixel comprises a transistor comprising a metal oxide in a channel formation region, and
wherein the metal oxide comprises In, the element M (M is at least one of Al, Ga, Y, and Sn), and Zn.

### Claim 9 (depends on 1)

The display device according to claim 1,
wherein the pixel comprises a transistor comprising silicon in a channel formation region.

### Claim 10

A display device comprising a first layer and a second layer over the first layer,
wherein the first layer comprises first circuits arranged in m rows and n columns (m and n are each an integer greater than or equal to 1 and a product of m and n is an integer greater than or equal to 2),
wherein the second layer comprises pixel blocks arranged in the m rows and the n columns,
wherein the pixel blocks each comprise pixels arranged in a rows and b columns (a and b are each an integer greater than or equal to 1),
wherein the pixel block comprises a first wiring and a second wiring electrically connected to the pixel,
wherein the first wiring and the second wiring included in the pixel block in an i-th row and a j-th column (i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n) are each electrically connected to the first circuit in the i-th row and the j-th column,
wherein the first wiring is configured to supply an input signal from the first circuit to the pixel,
wherein the second wiring is configured to supply an output signal from the pixel to the first circuit, and
wherein the pixel block in the i-th row and the j-th column has a region overlapping with the first circuit in the i-th row and the j-th column.