# US 12,120,897 B2 · Solid-state imaging element, electronic device, and manufacturing method of solid-state imaging element > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,120,897 B2 - Document ID: US12120897B2 - Status: Granted - Kind: B2 - Application number: 17/424,582 - Filed: 2020-01-21 - Published: 2022-03-17 - Granted: 2024-10-15 - Earliest claimed: 2019-01-28 - Assignees: Sony Group Corporation; Sony Semiconductor Solutions Corporation - Applicants: Sony Group Corporation; Sony Semiconductor Solutions Corporation - Inventors: Takushi Shigetoshi; Hideaki Togashi; Junpei Yamamoto; Shinpei Fukuoka; Moe Takeo; Sho Nishida - Web page: https://patentgrep.com/patent/US12120897B2 ## CPC - H10F 39/191: {Photoconductor image sensors} - H10K 39/32: Organic image sensors - H10F 39/026: {Wafer-level processing} - H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors - H10F 39/8023: {Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery} - H10F 39/80373: {characterised by the gate of the transistor} - H10F 39/807: {Pixel isolation structures} - H10F 39/812: {Arrangements for transferring the charges in the image sensor perpendicular to the imaging plane, e.g. buried regions used to transfer generated charges to circuitry under the photosensitive region} - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates} - H04N 25/70: SSIS architectures; Circuits associated therewith - H04N 25/76: Addressed sensors, e.g. MOS or CMOS sensors - H10F 39/014: {of CMOS image sensors} - H10F 39/199: {Back-illuminated image sensors} - H10F 39/811: {Interconnections} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A solid-state imaging element according to the present disclosure includes one or more photoelectric conversion layers, a penetrating electrode, and a connection pad. The one or more photoelectric conversion layers are provided on one principal surface side serving as a light incidence plane of a semiconductor substrate. The penetrating electrode is provided in a pixel area, connected at one end to the photoelectric conversion layer to penetrate through front and back surfaces of the semiconductor substrate, and transfers an electric charge photoelectrically converted by the photoelectric conversion layer, to a different principal surface side of the semiconductor substrate. The connection pad is provided on a same layer as gates (Ga, Gr, G1, and g2) of transistors (AMP, RST, TG1, and TG2) provided on the different principal surface side of the semiconductor substrate, and to which a different end of the penetrating electrode is connected. ## Claims ### Claim 1 A solid-state imaging element, comprising: one or more photoelectric conversion layers provided on one principal surface side serving as a light incidence plane of a semiconductor substrate; a penetrating electrode that is provided in a pixel area, connected at one end to the photoelectric conversion layer to penetrate through front and back surfaces of the semiconductor substrate, and configured to transfer an electric charge photoelectrically converted by the photoelectric conversion layer, to a different principal surface side of the semiconductor substrate; and a connection pad that is adjacent to and provided at a same level on the different principal surface side of the semiconductor substrate as a gate of an amplification transistor and to which a different end of the penetrating electrode is connected. ### Claim 2 (depends on 1) The solid-state imaging element according to claim 1, comprising: a Shallow Trench Isolation (STI) that is provided at a position facing the connection pad via a gate insulating film provided on the different principal surface of the semiconductor substrate, and surrounds a side circumferential surface of the different end side of the penetrating electrode. ### Claim 3 (depends on 1) The solid-state imaging element according to claim 1, wherein the connection pad is further connected with a floating diffusion to which the electric charge is transferred. ### Claim 4 (depends on 1) The solid-state imaging element according to claim 1, wherein the connection pad extends up to a position facing a channel formation region of the amplification transistor configured to amplify the electric charge, via a gate insulating film provided on the different principal surface of the semiconductor substrate, and functions as a gate of the amplification transistor. ### Claim 5 (depends on 1) The solid-state imaging element according to claim 1, wherein the connection pad extends up to a position contacting a floating diffusion to which the electric charge is transferred, and is bonded with the floating diffusion. ### Claim 6 (depends on 1) The solid-state imaging element according to claim 1, wherein a material of the connection pad is a same material as a gate of the amplification transistor. ### Claim 7 (depends on 1) The solid-state imaging element according to claim 1, wherein a material of the connection pad is a semiconductor doped with an impurity. ### Claim 8 (depends on 1) The solid-state imaging element according to claim 1, further comprising two or more photoelectric conversion layers provided on the one principal surface side serving as the light incidence plane of the semiconductor substrate. ### Claim 9 An electronic device, comprising: a solid-state imaging element, wherein the solid-state imaging element includes: one or more photoelectric conversion layers provided on one principal surface side serving as a light incidence plane of a semiconductor substrate; a penetrating electrode that is provided in a pixel area, connected at one end to the photoelectric conversion layer to penetrate through front and back surfaces of the semiconductor substrate, and configured to transfer an electric charge photoelectrically converted by the photoelectric conversion layer, to a different principal surface side of the semiconductor substrate; and a connection pad that is adjacent to and provided at a same level on the different principal surface side of the semiconductor substrate as a gate of an amplification transistor and to which a different end of the penetrating electrode is connected. ### Claim 10 (depends on 9) The electronic device according to claim 9, further comprising two or more photoelectric conversion layers provided on the one principal surface side serving as the light incidence plane of the semiconductor substrate. ### Claim 11 (depends on 9) The electronic device according to claim 9, comprising: a Shallow Trench Isolation (STI) that is provided at a position facing the connection pad via a gate insulating film provided on the different principal surface of the semiconductor substrate, and surrounds a side circumferential surface of the different end side of the penetrating electrode. ### Claim 12 (depends on 9) The electronic device according to claim 9, wherein the connection pad is connected with a floating diffusion to which the electric charge is transferred. ### Claim 13 (depends on 9) The electronic device according to claim 9, wherein the connection pad extends up to a position facing a channel formation region of the amplification transistor configured to amplify the electric charge, via a gate insulating film provided on the different principal surface of the semiconductor substrate, and functions as a gate of the amplification transistor. ### Claim 14 (depends on 9) The electronic device according to claim 9, wherein the connection pad extends up to a position contacting a floating diffusion to which the electric charge is transferred, and is bonded with the floating diffusion. ### Claim 15 (depends on 9) The electronic device according to claim 9, wherein a material of the connection pad is a same material as a gate of the transistor. ### Claim 16 (depends on 9) The electronic device according to claim 9, wherein a material of the connection pad is a semiconductor doped with an impurity. ### Claim 17 A manufacturing method of a solid-state imaging element, the manufacturing method comprising: a process of forming one or more photoelectric conversion layers on one principal surface side serving as a light incidence plane of a semiconductor substrate; a process of forming, in a pixel area, a penetrating electrode that is connected at one end to the photoelectric conversion layer to penetrate through front and back surfaces of the semiconductor substrate, and configured to transfer an electric charge photoelectrically converted by the photoelectric conversion layer, to a different principal surface side of the semiconductor substrate; and a process of forming a connection pad adjacent to and at a same level on the different principal surface side of the semiconductor substrate as a gate of an amplification transistor to which a different end of the penetrating electrode is connected. ### Claim 18 (depends on 17) The manufacturing method of a solid-state imaging element according to claim 17, wherein the manufacturing method further comprises a process of forming two or more photoelectric conversion layers on the one principal surface side serving as the light incidence plane of the semiconductor substrate. ### Claim 19 (depends on 17) The manufacturing method of a solid-state imaging element according to claim 17, wherein the manufacturing method further comprises a process of forming a Shallow Trench Isolation (STI) that is provided at a position facing the connection pad via a gate insulating film provided on the different principal surface of the semiconductor substrate, and surrounds a side circumferential surface of the different end side of the penetrating electrode. ### Claim 20 (depends on 17) The manufacturing method of a solid-state imaging element according to claim 17, wherein the manufacturing method further comprises a process connecting the connection pad with a floating diffusion to which the electric charge is transferred.