# US 12,120,886 B2 · Memory device and manufacturing method thereof

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- Number: US 12,120,886 B2
- Document ID: US12120886B2
- Status: Granted
- Kind: B2
- Application number: 17/461,355
- Filed: 2021-08-30
- Published: 2023-03-02
- Granted: 2024-10-15
- Earliest claimed: 2021-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Pei-Sheng Tang; Wei-De Ho; Han-Wei Wu; Yuan-Hsiang Lung; Hua-Tai Lin
- Web page: https://patentgrep.com/patent/US12120886B2

## CPC

- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/01: Manufacture or treatment
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 46/301: {for alignment}
- H10W 46/501: {for use before dicing}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a memory device includes forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region. A bottom via opening is formed in the dielectric layer and over the device region of the wafer and a trench is formed in the dielectric layer and over the peripheral region of the wafer. A bottom electrode via is formed in the bottom via opening. A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench. A memory layer and a top electrode are formed over the bottom electrode layer.

## Claims

### Claim 1

A method, comprising:
forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region;
forming a bottom via opening in the dielectric layer and over the device region of the wafer and a trench in the dielectric layer and over the peripheral region of the wafer;
forming a bottom electrode via in the bottom via opening, wherein forming the bottom electrode via is performed by a selectively growing process;
conformally forming a bottom electrode layer over the bottom electrode via and lining a sidewall and a bottom of the trench; and
forming a memory layer and a top electrode over the bottom electrode layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein conformally forming the bottom electrode layer is such that the bottom electrode layer is in contact with the sidewall of the trench.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the memory layer and the top electrode comprises:
forming a memory material layer over the bottom electrode layer; and
etching the memory material layer to form the memory layer over the device region of the wafer.

### Claim 4 (depends on 3)

The method of claim 3, wherein forming the memory material layer is such that a portion of the memory material layer over the peripheral region of the wafer is spaced apart from the dielectric layer.

### Claim 5 (depends on 3)

The method of claim 3, wherein forming the memory material layer is such that a bottommost portion of a top surface of the memory material layer is lower than a top surface of the dielectric layer.

### Claim 6 (depends on 3)

The method of claim 3, wherein forming the memory layer and the top electrode further comprises:
forming a top electrode layer over the memory material layer; and
etching the top electrode layer to form the top electrode over the device region of the wafer.

### Claim 7 (depends on 6)

The method of claim 6, wherein forming the top electrode layer is such that a bottommost portion of a top surface of the top electrode layer is lower than a top surface of the dielectric layer.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
forming a top electrode via on the top electrode.

### Claim 9

A method, comprising:
forming a dielectric layer over a wafer;
forming a bottom via opening and a trench in the dielectric layer;
forming a bottom electrode via in the bottom via opening;
sequentially forming a bottom electrode layer, a memory material layer, and a top electrode layer over the dielectric layer and in the trench;
forming a patterned mask over the top electrode layer by using a portion of the top electrode layer in the trench as an alignment mark; and
sequentially patterning the top electrode layer, the memory material layer, and the bottom electrode layer by using the patterned mask as an etching mask, wherein patterning the bottom electrode layer is such that the dielectric layer is exposed through the trench.

### Claim 10 (depends on 9)

The method of claim 9, wherein patterning the top electrode layer is such that a horizontal portion of the top electrode layer in the trench is removed while a vertical portion of the top electrode layer remains on a sidewall of the trench.

### Claim 11 (depends on 9)

The method of claim 9, wherein patterning the memory material layer is such that a horizontal portion of the memory material layer in the trench is removed while a vertical portion of the memory material layer remains on a sidewall of the trench.

### Claim 12 (depends on 9)

The method of claim 9, wherein patterning the bottom electrode layer is such that a sidewall of the patterned memory material layer is exposed through the trench.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
forming a spacer structure on the patterned memory material layer after patterning the bottom electrode layer.

### Claim 14

A method comprising:
forming a bottom electrode layer over a bottom electrode via and a trench in a first dielectric layer on a wafer;
sequentially forming a memory material layer and a top electrode layer over the bottom electrode layer;
forming a patterned mask over the top electrode layer by using a portion of the top electrode layer in the trench as an alignment mark;
patterning the top electrode layer, the memory material layer, and the bottom electrode layer by using the patterned mask as an etching mask; and
forming a spacer structure in contact with sidewalls of the bottom electrode layer and the memory material layer in the trench.

### Claim 15 (depends on 14)

The method of claim 14, wherein the bottom electrode layer is patterned such that the first dielectric layer is exposed through the trench.

### Claim 16 (depends on 14)

The method of claim 14, wherein the bottom electrode layer is patterned such that the sidewalls of the bottom electrode layer are in the trench.

### Claim 17 (depends on 14)

The method of claim 14, further comprising:
forming a second dielectric layer over the spacer structure and in contact with the first dielectric layer in the trench.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
forming a top via in the second dielectric layer and electrically connected to the top electrode layer on the bottom electrode via.

### Claim 19 (depends on 14)

The method of claim 14, wherein the memory material layer is disposed between the spacer structure and the bottom electrode layer.

### Claim 20 (depends on 14)

The method of claim 14, wherein the bottom electrode layer, the memory material layer and the spacer structure in the trench form an alignment structure.