# US 12,120,885 B2 · Ferroelectric tunnel junction memory device using a magnesium oxide tunneling dielectric and methods for forming the same

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- Number: US 12,120,885 B2
- Document ID: US12120885B2
- Status: Granted
- Kind: B2
- Application number: 18/354,858
- Filed: 2023-07-19
- Published: 2024-01-18
- Granted: 2024-10-15
- Earliest claimed: 2021-04-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Mauricio Manfrini; Bo-Feng Young; Chun-Chieh Li; Han-Jong Chia; Sai-Hooi Yeong
- Web page: https://patentgrep.com/patent/US12120885B2

## CPC

- H10B 51/30: characterised by the memory core region
- H10B 53/30: characterised by the memory core region
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/689: {having ferroelectric layers}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.

## Claims

### Claim 1

A method of manufacturing a ferroelectric tunnel junction (FTJ) memory device, the method comprising:
forming a layer stack including a bottom electrode material layer, ferroelectric tunnel junction material layers, and a top electrode material layer over a substrate, wherein the ferroelectric tunnel junction material layers comprise at least one ferroelectric material layer and at least one tunneling dielectric layer;
masking a region of the layer stack with an etch mask; and
forming a ferroelectric tunnel junction (FTJ) memory cell by etching unmasked portions of the layer stack that are not masked by the etch mask.

### Claim 2 (depends on 1)

The method of claim 1, wherein each of the at least one tunneling dielectric layer comprises polycrystalline magnesium oxide grains.

### Claim 3 (depends on 1)

The method of claim 1, wherein:
the etch mask comprises a patterned photoresist material portion; and
the unmasked portions of the layer stack are etched by performing an anisotropic etch process.

### Claim 4 (depends on 1)

The method of claim 1, further comprising forming a connection via structure formed within a connection-via-level dielectric layer over the substrate, wherein the layer stack is formed over the connection via structure.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
forming a dielectric material layer over, and around, the FTJ memory cell; and
forming a metal interconnect structure including a metal via portion through the dielectric material layer, wherein the metal interconnect structure contacts, or is electrically connected to, the top electrode that is a patterned portion of the top electrode material layer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
forming a first transistor over the substrate; and
forming a set of at least one metal interconnect structure formed within at least one dielectric material layer, wherein a bottom electrode formed by patterning the bottom electrode material layer is connected to the first transistor through the set of at least one metal interconnect structure.

### Claim 7 (depends on 1)

The method of claim 1, wherein the at least one tunneling dielectric layer comprises a plurality of tunneling dielectric layers.

### Claim 8 (depends on 1)

The method of claim 1, wherein the at least one ferroelectric material layer comprises a plurality of ferroelectric material layers.

### Claim 9 (depends on 8)

The method of claim 8, wherein:
each of the plurality of ferroelectric material layers comprises a ferroelectric material;
each of the at least one tunneling dielectric layer comprises a dielectric metal oxide that is different from the ferroelectric material; and
the plurality of ferroelectric material layers are vertically spaced apart from one another by the at least one tunneling dielectric layer.

### Claim 10 (depends on 1)

The method of claim 1, wherein the ferroelectric tunnel junction material layers comprise at least two repetitions of a layer stack including a tunneling dielectric layer and a ferroelectric material layer that are vertically stacked along a vertical direction such that each repetition among the at least two repetitions entirely overlies or entirely underlies any other repetition among the at least two repetitions.

### Claim 11

A method of manufacturing a ferroelectric tunnel junction (FTJ) memory device, the method comprising:
forming a layer stack including a bottom electrode material layer, ferroelectric tunnel junction material layers, and a top electrode material layer over a substrate, wherein the ferroelectric tunnel junction material layers comprise at least one ferroelectric material layer and at least one tunneling dielectric layer; and
patterning the layer stack into a two-dimensional array of ferroelectric tunnel junction memory cells, wherein each of the ferroelectric tunnel junction memory cells comprises a bottom electrode that is patterned portion of the bottom electrode material layer, a ferroelectric tunnel junction memory element that is a patterned portion of the ferroelectric tunnel junction material layers, and a top electrode that is a patterned portion of the top electrode material layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the at least one tunneling dielectric layer comprises a plurality of tunneling dielectric layers.

### Claim 13 (depends on 11)

The method of claim 11, wherein the at least one ferroelectric material layer comprises a plurality of ferroelectric material layers.

### Claim 14 (depends on 11)

The method of claim 11, wherein the ferroelectric tunnel junction material layers comprise at least two repetitions of a layer stack including a tunneling dielectric layer and a ferroelectric material layer that are vertically stacked along a vertical direction such that each repetition among the at least two repetitions entirely overlies or entirely underlies any other repetition among the at least two repetitions.

### Claim 15 (depends on 11)

The method of claim 11, further comprising forming field effect transistors comprising a respective semiconductor channel including a single crystalline semiconductor material of the substrate on the substrate, wherein the layer stack is formed above the field effect transistors.

### Claim 16 (depends on 11)

The method of claim 11, further comprising:
forming first dielectric material layers over the substrate; and
forming thin film transistors embedded in second dielectric material layers over the first dielectric material layers, wherein the layer stack is formed above the thin film transistors.

### Claim 17

A method of forming a ferroelectric tunnel junction (FTJ) memory array, the method comprising:
forming an array of transistors located on, or over, a substrate; and
forming a layer stack including a bottom electrode material layer, ferroelectric tunnel junction material layers, and a top electrode material layer over a substrate prior to, or after, formation of the array of transistors, wherein the ferroelectric tunnel junction material layers comprise at least one ferroelectric material layer and at least one tunneling dielectric layer; and
patterning the layer stack into a two-dimensional array of ferroelectric tunnel junction memory cells; and
providing electrical connections between the array of transistors and the two-dimensional array of ferroelectric tunnel junction memory cells such that each of the transistors comprises an access transistor for a respective one ferroelectric tunnel junction memory cell within the two-dimensional array of ferroelectric tunnel junction memory cells.

### Claim 18 (depends on 17)

The method of claim 17, wherein the at least one ferroelectric material layer comprises a plurality of ferroelectric material layers.

### Claim 19 (depends on 18)

The method of claim 18, wherein each of the plurality of ferroelectric material layers is laterally spaced apart from each other or among one another by the at least one tunneling dielectric layer.

### Claim 20 (depends on 17)

The method of claim 17, wherein the ferroelectric tunnel junction material layers comprise at least two repetitions of a layer stack including a tunneling dielectric layer and a ferroelectric material layer that are vertically stacked along a vertical direction such that each repetition among the at least two repetitions entirely overlies or entirely underlies any other repetition among the at least two repetitions.