# US 12,120,884 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 12,120,884 B2
- Document ID: US12120884B2
- Status: Granted
- Kind: B2
- Application number: 18/472,187
- Filed: 2023-09-21
- Published: 2024-01-11
- Granted: 2024-10-15
- Earliest claimed: 2021-08-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chia-Yu Ling; Katherine H. Chiang; Chung-Te Lin
- Web page: https://patentgrep.com/patent/US12120884B2

## CPC

- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 51/10: characterised by the top-view layout
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/033: {comprising ferroelectric layers}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a memory cell includes the following steps. A channel material is formed to contact a source line and a bit line. A ferroelectric (FE) material is formed to contact the channel material. A word line is formed to contact the FE material. The FE material is disposed between the channel material and the word line. The word line includes a bulk layer. The bulk layer includes a first metal layer and a second metal layer. The second metal layer is sandwiched between the first metal layer and the FE material.

## Claims

### Claim 1

A method of manufacturing a memory cell, the method comprising:
forming a channel material contacting a source line and a bit line;
forming a ferroelectric (FE) material contacting the channel material; and
forming a word line, wherein the FE material is disposed between the channel material and the word line, and the word line comprises a bulk layer, and the bulk layer comprises:
a first metal layer; and
a second metal layer, wherein the second metal layer is sandwiched between the first metal layer and the FE material.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second metal layer has an absolute value of the Gibbs energy of metal oxide formation lower than an absolute value of the Gibbs energy of metal oxide formation of the first metal layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first metal layer has a resistance value lower than a resistance value of the second metal layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the second metal layer has a width is equal to or less than a width of the first metal layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the second metal layer comprises:
a first part on a first sidewall of the first metal layer, wherein the first metal layer is separated from FE material by the first part; and
a second part on a second sidewall of the first metal layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the word line further comprises:
a first glue layer on a top surface of the first metal layer and top surfaces of the first part and second part of the second metal layer; and
a second glue layer on a bottom surface of the first metal layer and bottoms of the first part and second part of the second metal layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the word line comprises: a first conductive feature and a second conductive feature, wherein the first conductive feature and the second conductive feature each comprises the bulk layer, and the bulk layer comprises the first metal layer and the second metal layer.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first conductive feature and the second conductive feature each further comprises a glue layer on top and bottom surfaces of the first metal layer, on top and bottom surfaces of the second metal layer, and a sidewall the first metal layer which is away from the second metal layer.

### Claim 9

A method of manufacturing a semiconductor device, the method comprising:
providing a substrate;
forming a first memory cell over the substrate, the forming the first memory cell comprising forming a first thin film transistor, wherein the forming the first thin film transistor comprises:
forming a first word line, wherein the first word line comprises a first bulk layer, and the first bulk layer comprises:
a first metal layer; and
a second metal layer on a sidewall of the first metal layer; and
forming a ferroelectric (FE) material, wherein a first portion of the ferroelectric (FE) material contacts a sidewall of the second metal layer of the first word line, and the first metal layer is separated from the first portion of FE material by the second metal layer; and
forming a channel material, wherein a first portion of the channel material is disposed on sidewalls of the first portion the ferroelectric material, a source line and a bit line, wherein the FE material is disposed between the channel material and the second metal layer of the word line; and
forming a second memory cell over the first memory cell.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first metal layer comprises tungsten, cobalt, aluminum, nickel, copper, silver, gold, molybdenum, molybdenum nitride, or alloys thereof, and the second metal layer comprises ruthenium.

### Claim 11 (depends on 9)

The method of claim 9, wherein the second metal layer has a width equal to or less than a width of the first metal layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein a ratio of the width of the second metal layer to the width of the first metal layer is in the range of 0.1 to 1.0.

### Claim 13 (depends on 9)

The method of claim 9, wherein no dielectric interface layer is formed between first portion of the ferroelectric material and the second metal layer.

### Claim 14 (depends on 9)

The method of claim 9, wherein the forming the second memory cell comprises forming a second thin film transistor, and the second thin film transistor comprises:
a second word line separating from the first word line by a dielectric layer;
a second portion of the ferroelectric material contacting the second word line; and
a second portion of channel material contacting the second portion the ferroelectric material, the source line and the bit line, wherein the second word line comprises a second bulk layer, and the second bulk layer and the first bulk layer have same materials.

### Claim 15

A method of manufacturing a semiconductor device, the method comprising:
providing a first multilayer stack, the first multilayer stack comprising alternating dielectric layers and conductive layers, and the first multilayer stack has a first trench and a second trench therein;
removing portions of the conductive layers and thereby forming sidewall grooves at ends of the conductive layers; and
forming anti-oxidation layers in the sidewall grooves, wherein the anti-oxidation layers and the conductive layers form a plurality of word lines.

### Claim 16 (depends on 15)

The method of claim 15, wherein the anti-oxidation layers comprise ruthenium, and the conductive layers comprise tungsten, cobalt, aluminum, nickel, copper, silver, gold, molybdenum, molybdenum nitride, or alloys thereof, and the second metal layer.

### Claim 17 (depends on 15)

The method of claim 15, wherein the providing the first multilayer stack comprises:
providing a second multilayer stack, the second multilayer stack comprising alternating the dielectric layers and sacrificial layers;
patterning the second multilayer stack to form the first trench;
removing first portions of the sacrificial layers exposed by the first trench to form first sidewall recesses;
forming first conductive features in the first trench and the first sidewall recesses;
patterning the second multilayer stack to form the second trench;
removing second portions of the sacrificial layers exposed by the second trench to form second sidewall recesses;
forming second conductive features in the second trench and the second sidewall recesses; and
removing the first conductive features in the first trench and the second conductive features in the second trench.

### Claim 18 (depends on 15)

The method of claim 15, wherein the providing the first multilayer stack comprises:
providing a second multilayer stack, the second multilayer stack comprising alternating the dielectric layers and sacrificial layers;
patterning the second multilayer stack to form the first trench and a second trench at a same time;
removing the sacrificial layers exposed by the first trench and the second trench to form sidewall recesses;
forming conductive features in the first trench, the second trench, and the sidewall recesses; and
removing the conductive features in the first trench and the second trench.

### Claim 19 (depends on 15)

The method of claim 15, further comprising:
forming ferroelectric strips in the first trench and the second trench, wherein the ferroelectric strips are in contact with the anti-oxidation layers;
forming channel strips contacting the ferroelectric strips; and
forming source lines and bit lines contacting the channel strips.

### Claim 20 (depends on 15)

The method of claim 15, further comprising:
filling the first trench and the second trench with insulating layers;
forming openings in the insulating layers;
forming ferroelectric strips on sidewalls of the openings in the insulating layers;
forming channel strips contacting the ferroelectric strips; and
forming source lines and bit lines contacting the channel strips.