# US 12,120,883 B2 · Semiconductor memory device using a ferroelectric characteristic of charge storage layer and operating method thereof

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- Number: US 12,120,883 B2
- Document ID: US12120883B2
- Status: Granted
- Kind: B2
- Application number: 17/666,448
- Filed: 2022-02-07
- Published: 2022-08-25
- Granted: 2024-10-15
- Earliest claimed: 2021-02-25
- Assignees: Samsung Electronics Co., Ltd.; Research and Business Foundation Sungky
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sang-Yong Park; Jin-Hong Park; Sungjoo Lee
- Web page: https://patentgrep.com/patent/US12120883B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 51/30: characterised by the memory core region
- H10D 30/68: Floating-gate IGFETs
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/689: {having ferroelectric layers}
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B 51/40: characterised by the peripheral circuit region
- H10B 51/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor memory device capable of improving performance by the use of a charge storage layer including a ferroelectric material is provided. The semiconductor memory device includes a substrate, a tunnel insulating layer contacting the substrate, on the substrate, a charge storage layer contacting the tunnel insulating layer and including a ferroelectric material, on the tunnel insulating layer, a barrier insulating layer contacting the charge storage layer, on the charge storage layer, and a gate electrode contacting the barrier insulating layer, on the barrier insulating layer.

## Claims

### Claim 1

A semiconductor memory device comprising:
a substrate including second parts and a first part between the second parts;
a tunnel insulating layer including second parts and a first part between the second parts of the tunnel insulating layer, and contacting the first part of the substrate;
a charge storage layer contacting the first part of the tunnel insulating layer and including a ferroelectric material;
a barrier insulating layer filling space between two adjacent charge storage layers and contacting the second parts of the tunnel insulating layer and the charge storage layer; and
a gate electrode contacting the barrier insulating layer,
wherein the tunnel insulating layer, the charge storage layer, the barrier insulating layer, and the gate electrode are sequentially stacked on the substrate.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the barrier insulating layer extends along an upper surface and side surfaces of the charge storage layer, and
wherein the tunnel insulating layer extends along a part of a lower surface of the barrier insulating layer and a lower surface of the charge storage layer.

### Claim 3 (depends on 2)

The semiconductor memory device of claim 2, wherein the barrier insulating layer includes:
a first barrier insulating layer extending along an upper surface of the charge storage layer, and contacting the charge storage layer; and
a second barrier insulating layer extending along an upper surface of the first barrier insulating layer, and contacting the first barrier insulating layer and the gate electrode, and
wherein a material of the first barrier insulating layer is different from a material of the second barrier insulating layer.

### Claim 4 (depends on 2)

The semiconductor memory device of claim 2, wherein the tunnel insulating layer includes:
a first tunnel insulating layer extending along a lower surface of the charge storage layer, and contacting the charge storage layer; and
a second tunnel insulating layer extending along a lower surface of the first tunnel insulating layer, and contacting the first tunnel insulating layer, and
wherein a material of the first tunnel insulating layer is different from a material of the second tunnel insulating layer.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1, wherein the barrier insulating layer extends along an upper surface of the charge storage layer, and is not formed along side surfaces of the charge storage layer, and
wherein the tunnel insulating layer extends along a lower surface of the charge storage layer, and is not in contact with the barrier insulating layer.

### Claim 6 (depends on 1)

The semiconductor memory device of claim 1, wherein the barrier insulating layer includes:
a first barrier insulating layer extending along an upper surface of the charge storage layer, and contacting the charge storage layer; and
a second barrier insulating layer extending along an upper surface of the first barrier insulating layer, and contacting the first barrier insulating layer and the gate electrode, and
wherein a material of the first barrier insulating layer is different from a material of the second barrier insulating layer.

### Claim 7 (depends on 6)

The semiconductor memory device of claim 6, wherein the tunnel insulating layer includes:
a first tunnel insulating layer extending along a lower surface of the charge storage layer, and contacting the charge storage layer and a part of a lower surface of the first barrier insulating layer; and
a second tunnel insulating layer extending along a lower surface of the first tunnel insulating layer, and contacting the first tunnel insulating layer, and
wherein a material of the first tunnel insulating layer is different from a material of the second tunnel insulating layer.

### Claim 8 (depends on 1)

The semiconductor memory device of claim 1, wherein the tunnel insulating layer includes:
a first tunnel insulating layer extending along a lower surface of the charge storage layer, and contacting the charge storage layer; and
a second tunnel insulating layer extending along a lower surface of the first tunnel insulating layer, and contacting the first tunnel insulating layer, and
wherein a material of the first tunnel insulating layer is different from a material of the second tunnel insulating layer.

### Claim 9 (depends on 1)

The semiconductor memory device of claim 1, wherein the barrier insulating layer extends along an upper surface and side surfaces of the charge storage layer and side surfaces of the tunnel insulating layer.

### Claim 10 (depends on 9)

The semiconductor memory device of claim 9, wherein the barrier insulating layer includes a metal oxide.