US 12,120,881 B2Granted

Three-dimensional semiconductor devices

AssigneeSamsung Electronics Co., Ltd.

InventorsBongsoon Lim, Daeseok Byeon

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Abstract

Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.

Claims20

Dependent claims

A memory device comprising:

a memory cell region including a first metal pad on a first substrate;
a peripheral circuit region including a second metal pad on a second substrate and vertically connected to the memory cell region by the first metal pad and the second metal pad;
a memory cell array in the memory cell region including a plurality of cell strings including a plurality of memory cells, a plurality of word lines respectively connected to the plurality of memory cells, a plurality of bit lines connected to one side of the plurality of cell strings, and a ground selection line connected to the plurality of cell strings;
a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the plurality of cell strings and controlling a plurality of data program steps on the plurality of memory cells;
and
a row decoder in the peripheral circuit region for activating at least some of the plurality of word lines in response to a control of the control logic,
wherein the first substrate has a first crystal plane parallel to a first surface of the first substrate which faces the first metal pad,
wherein the second substrate has a second crystal plane parallel to a second surface of the second substrate which faces the second metal pad, and
wherein an arrangement direction of atoms of the first crystal plane that are exposed on the first surface of the first substrate intersects an arrangement direction of atoms of the second crystal plane that are exposed on the second surface of the second substrate.

6 more elements

A memory device comprising a cell structure and a peripheral circuit structure that are stacked on one another,

wherein the cell structure includes:
a plurality of gate electrodes that are stacked on a first surface of a first substrate;
a plurality of channel regions that vertically penetrates the plurality of gate electrodes;
a first interlayer insulating layer on the first surface of the first substrate, the first interlayer insulating layer covering the plurality of gate electrodes and the plurality of channel regions;
a plurality of first metal pads exposed on the first interlayer insulating layer, the plurality of first metal pads being connected to the plurality of gate electrodes and the plurality of channel regions;
and
a plurality of bit lines extending in a first direction,
wherein the peripheral circuit structure includes:
at least one transistor on a second surface of a second substrate;
a second interlayer insulating layer on the second surface of the second substrate, the second interlayer insulating layer covering the transistor;
and
a plurality of second metal pads exposed on the second interlayer insulating layer, the plurality of second metal pads being connected to the transistor,
wherein the peripheral circuit structure is vertically connected to the cell structure by the plurality of first metal pads and the plurality of second metal pads,
wherein a <100> crystal direction of the first substrate intersects a <100> crystal direction of the second substrate,
wherein the <110> crystal direction of the first substrate is the same as the first direction, and
wherein the <100> crystal direction of the second s st rate is the same as the first direction.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/931,500Filed 17 Jul 2020 · continuation in part
Priority: KR 10-2019-01114679 Sep 2019
Published: US 2021/0074716 A111 Mar 2021
Granted: 15 Oct 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10B 43/40
EEPROM devices comprising charge-trapping gate insulators: characterised by the peripheral circuit region
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
G11C 8/14
Arrangements for selecting an address in a digital store: word line organisation; Word line lay-out
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout

Family

Application16/835,484Parent of this continuation-in-part · filed 31 Mar 2020
US 2021/0074716 A1Pre-grant publication · published 11 Mar 2021
US 11,367,735 B2Parent of this continuation-in-part
US 2021/0074717 A1Published application
US 12,120,881 B2This patent

From the US filing history. Foreign family members aren’t listed.