# US 12,120,880 B1 · 3D semiconductor device and structure with logic and memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,120,880 B1 - Document ID: US12120880B1 - Status: Granted - Kind: B1 - Application number: 18/527,356 - Filed: 2023-12-03 - Published: 2024-10-17 - Granted: 2024-10-15 - Earliest claimed: 2015-10-24 - Assignees: Monolithic 3D Inc. - Applicants: Monolithic 3D Inc. - Inventors: Zvi Or-Bach; Jin-Woo Han - Web page: https://patentgrep.com/patent/US12120880B1 ## CPC - G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells} - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 11/406: Management or control of the refreshing or charge-regeneration cycles - G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency - G11C 11/5621: {using charge storage in a floating gate} - G11C 13/0002: {using resistive RAM [RRAM] elements} - G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 17/165: {Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002)} - G11C 29/702: {by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones} - H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells} - H10B 43/10: characterised by the top-view layout - H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors - H10D 62/121: {oriented parallel to substrates} - H10D 62/834: further characterised by the dopants - H10D 64/64: Electrodes comprising a Schottky barrier to a semiconductor - H10D 89/10: Integrated device layouts - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 2213/71: Three dimensional array - H10B 41/10: characterised by the top-view layout - H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 53/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 63/20: {comprising selection components having two electrodes, e.g. diodes} - H10B 63/34: {of the vertical channel field-effect transistor type} - H10B 63/845: {the switching components being connected to a common vertical conductor} - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 30/62: Fin field-effect transistors [FinFET] - H10N 70/20: Multistable switching devices, e.g. memristors - H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices} - H10N 70/8833: {Binary metal oxides, e.g. TaOx} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and at least one power-down control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array. ## Claims ### Claim 1 A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors; a first metal layer overlaying said first single crystal layer; a second metal layer overlaying said first metal layer; a third metal layer overlaying said second metal layer; a plurality of second transistors disposed atop said third metal layer; a plurality of third transistors disposed atop said plurality of second transistors; a fourth metal layer disposed atop said plurality of third transistors; a memory array comprising word-lines, wherein said memory array comprises at least four memory mini arrays, wherein each of said memory mini arrays comprises at least four rows by four columns of memory cells, wherein at least one of said plurality of second transistors comprises a metal gate, and wherein each of said memory cells comprises at least one of said plurality of second transistors or at least one of said plurality of third transistors; and a connection path from said fourth metal to said third metal, wherein said connection path comprises a via disposed through said memory array, and wherein said memory control circuit comprises at least one power down control circuit. ### Claim 2 (depends on 1) The 3D semiconductor device according to claim 1, wherein said memory control circuit is configured to control each of said four memory mini arrays independently. ### Claim 3 (depends on 1) The 3D semiconductor device according to claim 1, wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, being processed following a same lithography step. ### Claim 4 (depends on 1) The 3D semiconductor device according to claim 1, wherein said memory control circuit comprises at least one Look Up Table circuit (“LUT”). ### Claim 5 (depends on 1) The 3D semiconductor device according to claim 1, wherein said memory control circuit comprises at least one digital to analog converter circuit for each of said at least four memory mini arrays. ### Claim 6 (depends on 1) The 3D semiconductor device according to claim 1, further comprising: an upper level disposed atop said fourth metal layer, wherein said upper level comprises a mono-crystalline silicon layer. ### Claim 7 (depends on 1) The 3D semiconductor device according to claim 1, wherein said memory control circuit comprises at least one cache memory unit. ### Claim 8 A 3D semiconductor device, the device comprising: a first level comprising a single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors; a first metal layer overlaying said first single crystal layer; a second metal layer overlaying said first metal layer; a third metal layer overlaying said second metal layer; a plurality of second transistors disposed atop said third metal layer; a plurality of third transistors disposed atop said plurality of second transistors; a fourth metal layer disposed atop said plurality of third transistors; and a memory array comprising word-lines, wherein said memory array comprises at least four memory mini arrays, wherein each of said at least four memory mini arrays comprises at least four rows by at least four columns of memory cells, wherein at least one of said plurality of second transistors comprises a metal gate, wherein at least one of said plurality of second transistors comprises a structure deposited using Atomic Level Deposition (“ALD”), wherein each of said memory cells comprises at least one of said plurality of second transistors or at least one of said plurality of third transistors, and wherein said first level comprises at least one differential read circuit. ### Claim 9 (depends on 8) The 3D semiconductor device according to claim 8, wherein said memory control circuit is configured such that it is able to control each of said at least four memory mini arrays independently. ### Claim 10 (depends on 8) The 3D semiconductor device according to claim 8, wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, being processed following a same lithography step. ### Claim 11 (depends on 8) The 3D semiconductor device according to claim 8, wherein said first level comprises at least one in-out interface control circuit. ### Claim 12 (depends on 8) The 3D semiconductor device according to claim 8, wherein said memory control circuit comprises at least one logic counter circuit. ### Claim 13 (depends on 8) The 3D semiconductor device according to claim 8, further comprising: an upper level disposed atop said fourth metal layer, wherein said upper level comprises a mono-crystalline silicon layer. ### Claim 14 (depends on 8) The 3D semiconductor device according to claim 8, further comprising: a connection path between said fourth metal and said third metal, wherein said connection path comprises a via through said memory array. ### Claim 15 A 3D semiconductor device, the device comprising: a first level comprising a single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors; a first metal layer overlaying said first single crystal layer; a second metal layer overlaying said first metal layer; a third metal layer overlaying said second metal layer; a plurality of second transistors disposed atop said third metal layer; a plurality of third transistors disposed atop said plurality of second transistors; a fourth metal layer disposed atop said plurality of third transistors; a memory array comprising word-lines; and an upper level disposed atop said fourth metal layer, wherein said upper level comprises a mono-crystalline silicon layer, wherein said memory array comprises at least four memory mini arrays, wherein each of said at least four memory mini arrays comprises at least four rows by at least four columns of memory cells, wherein at least one of said plurality of second transistors comprises a metal gate, wherein each of said memory cells comprises at least one of said plurality of second transistors or at least one of said plurality of third transistors, and wherein said memory control circuit comprises at least one error correcting circuit. ### Claim 16 (depends on 15) The 3D semiconductor device according to claim 15, wherein said memory control circuit is configured such that it is able to control each of said at least four memory mini arrays independently. ### Claim 17 (depends on 15) The 3D semiconductor device according to claim 15, wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, being processed following a same lithography step. ### Claim 18 (depends on 15) The 3D semiconductor device according to claim 15, wherein said memory control circuit comprises at least one digital to analog converter circuit. ### Claim 19 (depends on 15) The 3D semiconductor device according to claim 15, wherein said memory control circuit comprises at least one cache memory circuit. ### Claim 20 (depends on 15) The 3D semiconductor device according to claim 15, wherein said memory control circuit comprises a memory refresh circuit.