# US 12,120,877 B2 · Semiconductor device including channel structure and through electrode, electronic system, and method of forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,120,877 B2 - Document ID: US12120877B2 - Status: Granted - Kind: B2 - Application number: 17/693,328 - Filed: 2022-03-12 - Published: 2023-03-02 - Granted: 2024-10-15 - Earliest claimed: 2021-09-02 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jinyoung Park; Hyuk Kim; Yeongeun Yook - Web page: https://patentgrep.com/patent/US12120877B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/40: characterised by the peripheral circuit region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10W 20/0696: {by using sacrificial placeholders, e.g. using sacrificial plugs} - H10W 20/42: Vias, e.g. via plugs - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a lower structure including lower wirings. A horizontal wiring layer is disposed on the lower structure while including a horizontal conductive layer, and a horizontal insulating layer extending through the horizontal conductive layer. A stack structure is disposed on the horizontal wiring layer. A channel structure extending into the horizontal wiring layer while extending through the stack structure is provided. A through electrode connected to the lower wirings while extending through the stack structure and the horizontal insulating layer is provided. The stack structure includes insulating layers and electrode layers repeatedly alternately stacked, and an interlayer insulating layer disposed at side surfaces of the insulating layers and the electrode layers. The through electrode includes a first portion extending into the interlayer insulating layer, and a second portion disposed between the first portion and the lower wirings while having a smaller horizontal width than the first portion. ## Claims ### Claim 1 A semiconductor device comprising: a lower structure comprising a plurality of lower wirings; a horizontal wiring layer disposed on the lower structure, the horizontal wiring layer comprising a horizontal conductive layer, and a horizontal insulating layer extending through the horizontal conductive layer; a stack structure on the horizontal wiring layer; a channel structure extending into the horizontal wiring layer while extending through the stack structure; and a through electrode connected to the plurality of lower wirings while extending through the stack structure and the horizontal insulating layer, wherein the stack structure comprises: a plurality of insulating layers and a plurality of electrode layers repeatedly alternately stacked, and an interlayer insulating layer disposed at side surfaces of the plurality of insulating layers and the plurality of electrode layers, and wherein the through electrode comprises: a first portion extending into the interlayer insulating layer, and a second portion disposed between the first portion and the plurality of lower wirings, the second portion having a smaller horizontal width than the first portion. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein a center of the second portion is misaligned from a center of the first portion. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the second portion extends through the interlayer insulating layer and the horizontal insulating layer. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein a distance between a first boundary between the first portion and the second portion and a bottom surface of the lower structure is greater than a distance between a lowermost end of the channel structure and the bottom surface of the lower structure. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein a distance between a first boundary between the first portion and the second portion and a bottom surface of the lower structure is smaller than a distance between a lowermost end of the plurality of electrode layers and the bottom surface of the lower structure. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein a distance between a first boundary between the first portion and the second portion and a bottom surface of the lower structure is greater than a distance between a lowermost end of the plurality of electrode layers and the bottom surface of the lower structure. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein: the plurality of insulating layers comprises a plurality of first insulating layers and a plurality of second insulating layers; the plurality of electrode layers comprises a plurality of first electrode layers and a plurality of second electrode layers; the interlayer insulating layer comprises a first interlayer insulating layer and a second interlayer insulating layer; the stack structure comprises: a first stack structure comprising the plurality of first insulating layers, the plurality of first electrode layers, and the first interlayer insulating layer, and a second stack structure disposed on the first stack structure, the second stack structure comprising the plurality of second insulating layers, the plurality of second electrode layers, and the second interlayer insulating layer; the through electrode further comprises: a third portion extending into the second interlayer insulating layer, and a fourth portion disposed between the third portion and the first portion, the fourth portion having a smaller horizontal width than the third portion; and the first portion extends into the first interlayer insulating layer. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein a center of the second portion is aligned with a center of the fourth portion. ### Claim 9 (depends on 7) The semiconductor device according to claim 7, wherein a center of the fourth portion is misaligned from a center of the third portion. ### Claim 10 (depends on 7) The semiconductor device according to claim 7, wherein the horizontal width of the second portion is substantially equal to the horizontal width of the fourth portion. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, further comprising: a cell contact plug connected to the plurality of lower wirings while extending through the plurality of insulating layers, the plurality of electrode layers, and the horizontal insulating layer, wherein the cell contact plug comprises: a fifth portion extending into the horizontal insulating layer while extending through the plurality of insulating layers and the plurality of electrode layers, and a sixth portion disposed between the fifth portion and the plurality of lower wirings, the sixth portion having a smaller horizontal width than the fifth portion, and wherein the cell contact plug is connected to a selected one of the plurality of electrode layers. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein a center of the sixth portion is misaligned from a center of the fifth portion. ### Claim 13 (depends on 11) The semiconductor device according to claim 11, wherein a distance between a second boundary between the fifth portion and the sixth portion and a bottom surface of the lower structure is smaller than a lowermost end of the channel structure and the bottom surface of the lower structure. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, further comprising: a source contact plug connected to the horizontal conductive layer while extending through the interlayer insulating layer, wherein the source contact plug comprises: a seventh portion extending into the interlayer insulating layer, and an eighth portion disposed between the seventh portion and the horizontal conductive layer, the eighth portion having a smaller horizontal width than the seventh portion. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein a center of the eighth portion is misaligned from a center of the seventh portion. ### Claim 16 A semiconductor device comprising: a lower structure comprising a plurality of lower wirings; a horizontal wiring layer disposed on the lower structure, the horizontal wiring layer comprising a horizontal conductive layer and a horizontal insulating layer extending through the horizontal conductive layer; a stack structure on the horizontal wiring layer; a channel structure extending into the horizontal wiring layer while extending through the stack structure; and a plurality of cell contact plugs connected to the plurality of lower wirings while extending through the stack structure and the horizontal insulating layer, wherein the stack structure comprises: a plurality of insulating layers and a plurality of electrode layers repeatedly alternately stacked, and an interlayer insulating layer disposed at side surfaces of the plurality of insulating layers and the plurality of electrode layers, wherein each of the plurality of cell contact plugs comprises: a first portion extending into the horizontal insulating layer while extending through the plurality of insulating layers and the plurality of electrode layers, and a second portion disposed between the first portion and the plurality of lower wirings, the second portion having a smaller horizontal width than the first portion, and wherein each of the plurality of cell contact plugs is connected to a corresponding one of the plurality of electrode layers. ### Claim 17 (depends on 16) The semiconductor device according to claim 16, wherein a center of the second portion is misaligned from a center of the first portion. ### Claim 18 (depends on 16) The semiconductor device according to claim 16, wherein a distance between a boundary between the first portion and the second portion and a bottom surface of the lower structure is smaller than a distance between a lowermost end of the channel structure and the bottom surface of the lower structure. ### Claim 19 (depends on 16) The semiconductor device according to claim 16, wherein: the plurality of insulating layers comprises a plurality of first insulating layers and a plurality of second insulating layers; the plurality of electrode layers comprises a plurality of first electrode layers and a plurality of second electrode layers; the interlayer insulating layer comprises a first interlayer insulating layer and a second interlayer insulating layer; the stack structure comprises: a first stack structure comprising the plurality of first insulating layers, the plurality of first electrode layers, and the first interlayer insulating layer, and a second stack structure disposed on the first stack structure, the second stack structure comprising the plurality of second insulating layers, the plurality of second electrode layers, and the second interlayer insulating layer; at least one of the plurality of cell contact plugs further comprises: a third portion extending into the second interlayer insulating layer, and a fourth portion disposed between the third portion and the first portion, the fourth portion having a smaller horizontal width than the third portion; and the first portion extends through the first interlayer insulating layer, the plurality of first insulating layers, and the plurality of first electrode layers. ### Claim 20 An electronic system comprising: a main substrate; a semiconductor device on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate, wherein the semiconductor device comprises: a lower structure comprising a plurality of lower wirings, a horizontal wiring layer disposed on the lower structure, the horizontal wiring layer comprising a horizontal conductive layer and a horizontal insulating layer extending through the horizontal conductive layer, a stack structure on the horizontal wiring layer, a channel structure extending into the horizontal wiring layer while extending through the stack structure, and a through electrode connected to the plurality of lower wirings while extending through the stack structure and the horizontal insulating layer, wherein the stack structure comprises: a plurality of insulating layers and a plurality of electrode layers repeatedly alternately stacked, and an interlayer insulating layer disposed at side surfaces of the plurality of insulating layers and the plurality of electrode layers, and wherein the through electrode comprises: a first portion extending into the interlayer insulating layer, and a second portion disposed between the first portion and the plurality of lower wirings, the second portion having a smaller horizontal width than the first portion.