# US 12,120,875 B2 · Storage unit and method of manufacturing the same and three-dimensional memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,120,875 B2 - Document ID: US12120875B2 - Status: Granted - Kind: B2 - Application number: 17/597,926 - Filed: 2019-07-29 - Published: 2022-08-18 - Granted: 2024-10-15 - Earliest claimed: 2019-07-29 - Assignees: Institute of Microelectronics, Chinese Academy of Sciences - Applicants: Institute of Microelectronics, Chinese Academy of Sciences - Inventors: Gang Zhang; Zongliang Huo - Web page: https://patentgrep.com/patent/US12120875B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A storage unit, a method of manufacturing the storage unit, and a three-dimensional memory. The storage unit includes: a first conductivity-type substrate; a channel layer stacked on the first conductivity-type substrate in a first direction; a second conductivity-type conduction layer including a first part and a second part that are connected, the first part being located between the first conductivity-type substrate and the channel layer, and the second part being formed in a via hole passing through the channel layer; a channel passage layer penetrating the channel layer and the first part in a negative direction of the first direction, and extending into an interior of the first conductivity-type substrate; and an insulating layer located in the channel layer and surrounding a periphery of the channel passage layer. The first conductivity-type substrate and the second conductivity-type conduction layer provide carriers required for reading and erasing operations, respectively. ## Claims ### Claim 1 A storage unit, comprising: a first conductivity-type substrate; a channel layer stacked on the first conductivity-type substrate in a first direction; a second conductivity-type conduction layer comprising a first part and a second part that are connected, the first part being located between the first conductivity-type substrate and the channel layer, and the second part being formed in a via hole passing through the channel layer; a channel passage layer penetrating the channel layer and the first part of the second conductivity-type conduction layer in a negative direction of the first direction, and extending into an interior of the first conductivity-type substrate; and an insulating layer located in the channel layer and surrounding a periphery of the channel passage layer, wherein a surface of the insulating layer facing the first conductivity-type substrate and in contact with the first part of the second conductivity-type conduction layer is flush with a bottommost surface of the channel layer facing the first conductivity-type substrate and in contact with the first part of the second conductivity-type conduction layer, and wherein the first conductivity-type substrate is a p-type substrate, and the second conductivity- type conduction layer is an n-type conduction layer, the first conductivity-type substrate is configured to provide a hole pumped into the channel passage layer so as to achieve an erasing operation, and the second conductivity-type conduction layer is configured to provide an electron pumped into the channel passage layer to achieve a reading operation. ### Claim 2 (depends on 1) The storage unit according to claim 1, wherein the channel layer comprises a plurality of stack pairs, and each of the plurality of stack pairs comprises a first stack material and a second stack material. ### Claim 3 (depends on 2) The storage unit according to claim 2, wherein the first stack material is silicon oxide, and the second stack material is silicon nitride. ### Claim 4 (depends on 1) The storage unit according to claim 1, wherein the insulating layer is a sandwich structure comprising a first sandwich material, a second sandwich material, and a third sandwich material. ### Claim 5 (depends on 4) The storage unit according to claim 4, wherein the first sandwich material, the second sandwich material, and the third sandwich material are silicon oxide, silicon nitride and silicon oxide, respectively. ### Claim 6 (depends on 1) The storage unit according to claim 1, wherein an ion concentration of the first part and an ion concentration of the second part are the same or different. ### Claim 7 A method of manufacturing a storage unit, comprising: preparing a first conductivity-type substrate; forming a channel layer stacked on the first conductivity-type substrate in a first direction; forming a second conductivity-type conduction layer comprising a first part and a second part that are connected, the first part being located between the first conductivity-type substrate and the channel layer, and the second part being formed in a via hole passing through the channel layer; forming a channel passage layer, wherein the channel passage layer penetrates the channel layer and the first part of the second conductivity-type conduction layer in a negative direction of the first direction, and extends into an interior of the first conductivity- type substrate; and forming an insulating layer located in the channel layer, wherein the insulating layer surrounds a periphery of the channel passage layer, wherein a surface of the insulating layer facing the first conductivity-type substrate and in contact with the first part of the second conductivity-type conduction layer is flush with a bottommost surface of the channel layer facing the first conductivity-type substrate and in contact with the first part of the second conductivity-type conduction layer, and wherein the first conductivity-type substrate is a p-type substrate, and the second conductivity-type conduction layer is an n-type conduction layer, the first conductivity-type substrate is configured to provide a hole pumped into the channel passage layer so as to achieve an erasing operation, and the second conductivity-type conduction layer is configured to provide an electron pumped into the channel passage layer to achieve a reading operation. ### Claim 8 (depends on 7) The method according to claim 7, in a process of forming the second conductivity-type conduction layer, a substrate of the storage unit is placed upwardly to form the second conductivity-type conduction layer. ### Claim 9 (depends on 1) A three-dimensional memory, comprising the storage unit according to claim 1.