# US 12,120,873 B2 · Three-dimensional flash memory and method of forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,120,873 B2 - Document ID: US12120873B2 - Status: Granted - Kind: B2 - Application number: 17/483,505 - Filed: 2021-09-23 - Published: 2023-03-23 - Granted: 2024-10-15 - Earliest claimed: 2021-09-23 - Assignees: Macronix International Co., Ltd. - Applicants: MACRONIX International Co., Ltd. - Inventors: Chia-Tze Huang - Web page: https://patentgrep.com/patent/US12120873B2 ## CPC - H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/10: characterised by the top-view layout - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/10: characterised by the top-view layout - H10B 43/35: with cell select transistors, e.g. NAND - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Provided is a three-dimensional flash memory including a substrate, a stack structure, a stop layer, two slit trenches, a plurality of vertical channel structures, and a plurality of slit holes. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The stop layer is disposed between the substrate and the stack structure. The two slit trenches penetrate through the stack structure to expose the stop layer. The vertical channel structures are disposed between the two slit trenches and penetrate through the stack structure and the stop layer. The slit holes are discretely disposed between the vertical channel structures, and penetrate through the stack structure to expose the stop layer. A method of forming the three-dimensional flash memory is also provided. ## Claims ### Claim 1 A three-dimensional (3D) flash memory, comprising: a substrate; a stack structure, disposed on the substrate, wherein the stack structure comprises a plurality of dielectric layers and a plurality of conductive layers stacked alternately; two adjacent slit trenches, penetrating through the stack structure, wherein the two adjacent slit trenches have an average width 30w; a plurality of vertical channel structures, disposed between the two adjacent slit trenches, and penetrating through the stack structure; and a plurality of slit holes, discretely disposed between the plurality of vertical channel structures, and penetrating through the stack structure, wherein the plurality of slit holes have an average width W greater than or equal to the average width 30w of the two adjacent slit trenches. ### Claim 2 (depends on 1) The 3D flash memory according to claim 1, wherein the two adjacent slit trenches extend along a first direction and the plurality of slit holes are arranged along in the first direction. ### Claim 3 (depends on 1) The 3D flash memory according to claim 1, wherein the plurality of slit holes is a strip shape, an average length L of the plurality of slit holes being greater than three times the average width W thereof. ### Claim 4 (depends on 1) The 3D flash memory according to claim 1, wherein a distance between the two adjacent slit trenches is between 1 μm and 20 μm. ### Claim 5 (depends on 1) The 3D flash memory according to claim 1, wherein each of the plurality of vertical channel structures includes a first S/D pillar and a second S/D pillar laterally surrounded by a channel layer. ### Claim 6 (depends on 1) The 3D flash memory according to claim 1, further comprising a plurality of conductive features respectively disposed in the two slit trenches and the plurality of slit holes. ### Claim 7 (depends on 1) The 3D flash memory according to claim 1, wherein each of the plurality of vertical channel structures includes a channel layer laterally surrounded by a charge storage layer. ### Claim 8 (depends on 1) The 3D flash memory according to claim 1, wherein a shape of the plurality of slit holes in a top view includes a dot shape, a strip shape or a combination thereof. ### Claim 9 (depends on 1) The 3D flash memory according to claim 1, wherein when a shape of the plurality of slit holes is a dot shape, the plurality of slit holes have an average diameter greater than or equal to an average width of the two slit trenches, and the average diameter of the plurality of slit holes is greater than or equal to an average diameter of the plurality of vertical channel structures. ### Claim 10 (depends on 1) The 3D flash memory according to claim 1, wherein the average width of the plurality of slit holes is greater than or equal to an average diameter of the plurality of vertical channel structures. ### Claim 11 (depends on 1) The 3D flash memory according to claim 1, wherein the plurality of slit holes are arranged in a single-line configuration or a multi-line configuration in a top view. ### Claim 12 A method of forming a three-dimensional (3D) flash memory, comprising: forming a stop layer and a stack structure on a substrate, wherein the stack structure comprises a plurality of dielectric layers and a plurality of sacrificial layers stacked alternately; forming a plurality of first openings in the stack structure and the stop layer; respectively forming a plurality of vertical channel structures in the plurality of first openings; forming a plurality of second openings exposing the stop layer in the stack structure, wherein the plurality of second openings at least comprise two adjacent slit trenches having an average width 30w and a plurality of slit holes having have an average width W, the plurality of vertical channel structures are formed between the two slit trenches, and the plurality of slit holes are discretely formed between the plurality of vertical channel structures, wherein the average width W of the plurality of slit holes is greater than or equal to the average width 30w of the two adjacent slit trenches; and performing a gate replacement process through the plurality of second openings, so that the plurality of sacrificial layers are replaced by a plurality of conductive layers. ### Claim 13 (depends on 12) The method of forming the 3D flash memory according to claim 12, wherein the two slit trenches extend along a first direction and the plurality of slit holes are arranged along in the first direction. ### Claim 14 (depends on 12) The method of forming the 3D flash memory according to claim 12, wherein the plurality of slit holes is a strip shape, an average length L of the plurality of slit openings being greater than three times the average width W. ### Claim 15 (depends on 12) The method of forming the 3D flash memory according to claim 12, wherein each vertical channel structure comprises: two source/drain (S/D) pillars, penetrating through the stack structure and the stop layer; and a channel layer, surrounding the two S/D pillars. ### Claim 16 (depends on 12) The method of forming the 3D flash memory according to claim 12, wherein a shape of the plurality of slit holes in a top view includes a dot shape, a strip shape or a combination thereof. ### Claim 17 (depends on 12) The method of forming the 3D flash memory according to claim 12, wherein when a shape of the plurality of slit holes is a dot shape, the plurality of slit holes have an average diameter greater than or equal to an average width of the two slit trenches, and the average diameter of the plurality of slit holes is greater than or equal to an average diameter of the plurality of vertical channel structures. ### Claim 18 (depends on 12) The method of forming the 3D flash memory according to claim 12, wherein a removal limitation area of one of the plurality of slit holes for removing the plurality of sacrificial layers in the gate replacement process is partially overlapped with a removal limitation area of one of the two slit trenches for removing the plurality of sacrificial layers in the gate replacement process. ### Claim 19 (depends on 12) The method of forming the 3D flash memory according to claim 12, wherein a distance between the two adjacent slit trenches is between 1 μm and 20 μm. ### Claim 20 (depends on 12) The method of forming the 3D flash memory according to claim 12, wherein the average width of the plurality of slit holes is greater than or equal to an average diameter of the plurality of vertical channel structures.