# US 12,120,871 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 12,120,871 B2
- Document ID: US12120871B2
- Status: Granted
- Kind: B2
- Application number: 17/153,610
- Filed: 2021-01-20
- Published: 2021-05-13
- Granted: 2024-10-15
- Earliest claimed: 2016-06-27
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Nam Jae Lee
- Web page: https://patentgrep.com/patent/US12120871B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B 99/00: Subject matter not provided for in other groups of this subclass
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first cell structure and the second cell structure, and may be electrically coupled to the first and second cell structures. The pad structure may have a plurality of stepped structures. The circuit may be disposed under the pad structure. The one or more openings may pass through the pad structure, and may expose the circuit. The one or more openings may be disposed between the plurality of stepped structures.

## Claims

### Claim 1

A semiconductor device, comprising:
a circuit;
a pad structure located over the circuit, the pad structure comprising a first stepped structure including first pads stacked on top of one another, a second stepped structure including second pads stacked on top of one another, and a third stepped structure including third pads stacked on top of one another;
a first interconnection structure electrically coupling the first pads and the third pads to each other and coupling the first and third pads to the circuit through a first opening; and
a second interconnection structure electrically coupling the second pads to each other and coupling the second pads to the circuit through a second opening.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first line structure including first lines stacked on top of one another, the first lines being electrically coupled to the respective first pads;
a second line structure including second lines stacked on top of one another, the second lines being electrically coupled to the respective second pads; and
a third line structure including third lines stacked on top of one another, the third lines being electrically coupled to the respective third pads,
wherein, among the first to third lines, first to third lines that are disposed at the same level are insulated from each other.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising:
a first cell structure including first source select lines stacked on top of one another and second source select lines stacked on top of one another, the first cell structure being formed such that, among the first and second source select lines, a first source select line and a second source select line that are disposed at the same level are insulated from each other; and
a second cell structure including third source select lines stacked on top of one another and fourth source select lines stacked on top of one another, the second cell structure being formed such that, among the third and fourth source select lines, a third source select line and a fourth source select line that are disposed at the same level are insulated from each other,
wherein the first lines are electrically coupled to the respective second source select lines, each of the second lines is coupled in common, among the first and third source select lines, to a first source select line and a third source select line that are disposed at the same level, and the third lines are electrically coupled to the respective fourth source select lines.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first opening is located between the first stepped structure and the second stepped structure.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second opening is located between the second stepped structure and the third stepped structure.