# US 12,120,870 B2 · Semiconductor device and method for manufacturing semiconductor device

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- Number: US 12,120,870 B2
- Document ID: US12120870B2
- Status: Granted
- Kind: B2
- Application number: 17/466,213
- Filed: 2021-09-03
- Published: 2022-06-16
- Granted: 2024-10-15
- Earliest claimed: 2020-12-15
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Kohei Nakagami
- Web page: https://patentgrep.com/patent/US12120870B2

## CPC

- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

According to one embodiment, a semiconductor device includes a first region including a memory cell and a second region including a peripheral circuit. The second region includes a diffusion region provided on a surface of the semiconductor layer, a gate insulating film provided on the diffusion region, a gate electrode provided on the gate insulating film, an insulator layer provided on the diffusion region and surrounding the gate electrode, and an element isolation that is embedded in the semiconductor layer and surrounds the diffusion region. The element isolation includes a first region that is recessed below the surface of the diffusion region and a second region that is between the diffusion region and the first region and includes a protrusion protruding to a level higher than the first region.

## Claims

### Claim 1

A semiconductor device, comprising:
a first region including a memory cell; and
a second region including a peripheral circuit, wherein
the second region includes:
a diffusion region at a surface of a semiconductor layer,
a gate insulating film on a surface of the diffusion region,
a gate electrode on the gate insulating film,
an element isolation region embedded in the semiconductor layer and surrounding the diffusion region,
a gate spacer insulator on the surface of the diffusion region, the element isolation region, and a sidewall surface of the gate electrode, the gate spacer insulator surrounding the gate electrode, and
the element isolation region having an upper surface that includes:
a first portion recessed to a level lower than the surface of the diffusion region, and
a second portion between the diffusion region and the first portion and including a protrusion protruding to a level greater than the level of the first portion.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the protrusion protrudes to a level higher than the surface of the diffusion region.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the element isolation region overlaps a portion of the diffusion region.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the element isolation region overlaps a sidewall portion of the diffusion region.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the protrusion directly contacts the gate spacer insulator.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein the protrusion protrudes to a level higher than the surface of the diffusion region.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the second portion of the upper surface of the element isolation region overlaps an outer edge of the diffusion region.

### Claim 8

A storage device, comprising:
a semiconductor layer;
a plurality memory cells on the semiconductor layer in a first region; and
a peripheral circuit formed on the semiconductor layer in a second region that is adjacent to the first region in a first direction, wherein
the peripheral circuit includes a transistor comprising:
a well region at a surface of the semiconductor layer;
a gate insulating film on a surface of the well region;
a gate electrode on the gate insulating film;
an element isolation structure embedded in the semiconductor layer and surrounding the well region; and
a gate spacer insulator on the surface of the well region, the element isolation structure, and a sidewall surface of the gate electrode, the gate spacer insulator surrounding the gate electrode, wherein the element isolation structure has an upper surface that includes:
a first portion recessed to a level lower than the surface of the well region, and
a second portion between the well region and the first portion and including a protrusion protruding to a level greater than the level of the first portion.

### Claim 9 (depends on 8)

The storage device according to claim 8, wherein the protrusion protrudes to a level higher than the surface of the well region.

### Claim 10 (depends on 9)

The storage device according to claim 9, wherein the element isolation structure overlaps a portion of the well region.

### Claim 11 (depends on 8)

The storage device according to claim 8, wherein the element isolation structure overlaps a sidewall portion of the well region.

### Claim 12 (depends on 8)

The storage device according to claim 8, wherein the protrusion directly contacts the gate spacer insulator.

### Claim 13 (depends on 12)

The storage device according to claim 12, wherein the protrusion protrudes to a level higher than the surface of the well region.

### Claim 14 (depends on 8)

The storage device according to claim 8, wherein the second portion of the upper surface of the element isolation structure overlaps to the surface of the well region.

### Claim 15 (depends on 8)

The storage device according to claim 8, wherein the well region is doped with p-type dopants.

### Claim 16 (depends on 8)

The storage device according to claim 8, wherein the well region is doped with n-type dopants.

### Claim 17

A method of manufacturing a semiconductor device, the method comprising:
forming an insulating film on an upper surface of diffusion region that is in a semiconductor layer;
forming a semiconductor film on the insulating film;
forming an element isolation structure extending through the semiconductor film and insulating film into the semiconductor layer, the element isolation structure surrounding the diffusion region;
forming a recess in an upper surface of the element isolation structure by removing a part of the element isolation structure;
forming a conductive film on the semiconductor film and the recessed upper surface of the element isolation structure;
forming a gate electrode by removing portions of the insulating film, the semiconductor film, and the conductive film; and
forming a gate spacer insulator on the upper surface of the diffusion region to surround the gate electrode, the gate spacer insulator directly contacting the element isolation structure and being on a sidewall surface of the gate electrode, wherein
in forming the gate electrode, a first region of the element isolation structure is recessed to be lower than the upper surface of the diffusion region and a second region of the element isolation structure includes a protruding portion that protrudes to a level higher than the upper surface of the diffusion region, the second region being between the first region and the diffusion region and directly adjacent to the diffusion region.

### Claim 18 (depends on 17)

The method according to claim 17, wherein the protruding portion directly contacts the gate spacer insulator.

### Claim 19 (depends on 17)

The method according to claim 17, wherein the element isolation structure overlaps the upper surface of the diffusion region.

### Claim 20 (depends on 17)

The method according to claim 17, wherein the element isolation structure directly contacts the upper surface of the diffusion region.