# US 12,120,864 B2 · Memory device using semiconductor element

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- Number: US 12,120,864 B2
- Document ID: US12120864B2
- Status: Granted
- Kind: B2
- Application number: 17/970,836
- Filed: 2022-10-21
- Published: 2023-02-09
- Granted: 2024-10-15
- Earliest claimed: 2020-12-25
- Assignees: Unisantis Electronics Singapore Pte. Ltd.
- Applicants: Unisantis Electronics Singapore Pte. Ltd.
- Inventors: Koji Sakui; Nozomu Harada
- Web page: https://patentgrep.com/patent/US12120864B2

## CPC

- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C 16/02: electrically programmable
- G11C 16/10: Programming or data input circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/32: Timing circuits
- G11C 2211/4016: Memory devices with silicon-on-insulator cells
- H10B 12/05: {Making the transistor}
- H10B 12/33: {the capacitor extending under the transistor}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device includes pages containing memory cells arranged in an array on a substrate. In each memory cell, a voltage applied to a first gate conductor layer, second gate conductor layer, third gate conductor layer, first impurity layer, and second impurity layer is controlled to form a hole group by impact ionization inside a channel semiconductor layer, and a page write operation of holding the hole group and a page erase operation of removing the hole group are performed. The first impurity layer is connected to a source line, the second impurity layer to a bit line, the first gate conductor layer to a first plate line, the second gate conductor layer to a second plate line, and the third gate conductor layer to a word line. A page erase operation is performed without inputting a positive or negative bias pulse to the bit line and the source line.

## Claims

### Claim 1

A memory device using a semiconductor element in which a page is composed of a plurality of memory cells arrayed on a substrate in a row direction, and a plurality of pages are arrayed in a column direction,
each of the memory cells included in each of the pages comprising:
a semiconductor base standing on the substrate in a vertical direction relative to the substrate or extending on the substrate in a horizontal direction relative to the substrate;
a first impurity layer and a second impurity layer at two ends of the semiconductor base;
a first gate insulating layer surrounding a portion or all of a side surface of the semiconductor base between the first impurity layer and the second impurity layer, the first gate insulating layer being in contact with or proximate to the first impurity layer;
a second gate insulating layer surrounding the side surface of the semiconductor base, being connected to the first gate insulating layer, and being in contact with or proximate to the second impurity layer;
a first gate conductor layer and a second gate conductor layer covering two opposite side surfaces of the first gate insulating layer while being separate from each other;
a third gate conductor layer covering the second gate insulating layer; and
a channel semiconductor layer of the semiconductor base covered with the first gate insulating layer and the second gate insulating layer, wherein:
a voltage applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the first impurity layer, and the second impurity layer is controlled to form a hole group by impact ionization inside the channel semiconductor layer, and the hole group is held;
in a page write operation, a voltage of the channel semiconductor layer is set to a first data holding voltage that is higher than a voltage of one or both of the first impurity layer and the second impurity layer;
in a page erase operation, a voltage applied to the first impurity layer, the second impurity layer, the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer is controlled to extract the hole group from one or both of the first impurity layer and the second impurity layer, and the voltage of the channel semiconductor layer is set to a second data holding voltage that is lower than the first data holding voltage;
of the memory cell, the first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, the first gate conductor layer is connected to a first plate line, the second gate conductor layer is connected to a second plate line, and the third gate conductor layer is connected to a word line;
in the page erase operation, the hole group in the channel semiconductor layer is extracted from one or both of the first impurity layer and the second impurity layer by lowering the second plate line from a first voltage to a second voltage at a first time, raising the first plate line from a third voltage to a fourth voltage and raising a voltage of the word line from a fifth voltage to a sixth voltage at a second time, and returning the second plate line from the second voltage to the first voltage at a third time; and
the voltage of the channel semiconductor layer, to which the first plate line and the word line are capacitively coupled, is lowered to the second data holding voltage by returning the first plate line from the fourth voltage to the third voltage and returning the voltage of the word line from the sixth voltage to the fifth voltage at a fourth time.

### Claim 2 (depends on 1)

The memory device using the semiconductor element according to claim 1, wherein:
one or both of the first plate line and the second plate line of the memory cells arrayed in the row direction and the column direction are disposed to be shared by the adjacent memory cells.

### Claim 3 (depends on 1)

The memory device using the semiconductor element according to claim 1, wherein:
one or both of the first voltage and the fifth voltage are a ground voltage.

### Claim 4 (depends on 3)

The memory device using the semiconductor element according to claim 3, wherein:
the second voltage is a negative voltage lower than the ground voltage.

### Claim 5 (depends on 1)

The memory device using the semiconductor element according to claim 1, wherein:
a total capacitance of a first gate capacitance between the first gate conductor layer and the channel semiconductor layer and a second gate capacitance between the second gate conductor layer and the channel semiconductor layer is larger than a third gate capacitance between the third gate conductor layer and the channel semiconductor layer.

### Claim 6 (depends on 1)

The memory device using the semiconductor element according to claim 1, wherein:
when viewed from an axial direction of the semiconductor base, the first gate conductor layer and the second gate conductor layer are opposite and separate from each other while surrounding the first gate insulating layer.

### Claim 7 (depends on 1)

The memory device using the semiconductor element according to claim 1, wherein:
the impact ionization occurs inside the channel semiconductor layer between the first gate conductor layer and the third gate conductor layer, and generates the hole group inside the channel semiconductor layer.

### Claim 8 (depends on 1)

The memory device using the semiconductor element according to claim 1, wherein:
the source line is separated every memory cells arrayed in the column direction, and is arranged parallel to the word line, the first plate line, and the second plate line.

### Claim 9 (depends on 1)

The memory device using the semiconductor element according to claim 1, wherein:
in an all-page erase operation, an all-page selection signal is input to a row decoder circuit, and all the pages are selected and erased.

### Claim 10 (depends on 1)

The memory device using the semiconductor element according to claim 1, wherein:
in the page erase operation, a fixed voltage is applied as a voltage of the source line and the bit line.

### Claim 11

A memory device using a semiconductor element in which a page is composed of a plurality of memory cells arrayed on a substrate in a row direction, and a plurality of pages are arrayed in a column direction,
each of the memory cells included in each of the pages comprising:
a semiconductor base standing on the substrate in a vertical direction relative to the substrate or extending on the substrate in a horizontal direction relative to the substrate;
a first impurity layer and a second impurity layer at two ends of the semiconductor base;
a first gate insulating layer surrounding a side surface of the semiconductor base between the first impurity layer and the second impurity layer, the first gate insulating layer being in contact with or proximate to the first impurity layer;
a second gate insulating layer surrounding a portion or all of the side surface of the semiconductor base, being connected to the first gate insulating layer, and being in contact with or proximate to the second impurity layer;
a first gate conductor layer and a second gate conductor layer covering two opposite side surfaces of the second gate insulating layer while being separate from each other;
a third gate conductor layer covering the first gate insulating layer; and
a channel semiconductor layer of the semiconductor base covered with the first gate insulating layer and the second gate insulating layer, wherein:
a voltage applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the first impurity layer, and the second impurity layer is controlled to form a hole group by impact ionization inside the channel semiconductor layer, and the hole group is held;
in a page write operation, a voltage of the channel semiconductor layer is set to a first data holding voltage that is higher than a voltage of one or both of the first impurity layer and the second impurity layer;
in a page erase operation, a voltage applied to the first impurity layer, the second impurity layer, the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer is controlled to extract the hole group from one or both of the first impurity layer and the second impurity layer, and the voltage of the channel semiconductor layer is set to a second data holding voltage that is lower than the first data holding voltage;
of the memory cell, the first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, the first gate conductor layer is connected to a first plate line, the second gate conductor layer is connected to a second plate line, and the third gate conductor layer is connected to a word line;
in the page erase operation, the hole group in the channel semiconductor layer is extracted from one or both of the first impurity layer and the second impurity layer by lowering the second plate line from a first voltage to a second voltage at a first time, raising the first plate line from a third voltage to a fourth voltage and raising a voltage of the word line from a fifth voltage to a sixth voltage at a second time, and returning the second plate line from the second voltage to the first voltage at a third time; and
the voltage of the channel semiconductor layer, to which the first plate line and the word line are capacitively coupled, is lowered to the second data holding voltage by returning the first plate line from the fourth voltage to the third voltage and returning the voltage of the word line from the sixth voltage to the fifth voltage at a fourth time.

### Claim 12 (depends on 11)

The memory device using the semiconductor element according to claim 11, wherein:
one or both of the first plate line and the second plate line of the memory cells arrayed in the row direction and the column direction are disposed to be shared by the adjacent memory cells.

### Claim 13 (depends on 11)

The memory device using the semiconductor element according to claim 11, wherein:
one or both of the first voltage and the fifth voltage are a ground voltage.

### Claim 14 (depends on 13)

The memory device using the semiconductor element according to claim 13, wherein:
the second voltage is a negative voltage lower than the ground voltage.

### Claim 15 (depends on 11)

The memory device using the semiconductor element according to claim 11, wherein:
a total capacitance of a first gate capacitance between the first gate conductor layer and the channel semiconductor layer and a second gate capacitance between the second gate conductor layer and the channel semiconductor layer is larger than a third gate capacitance between the third gate conductor layer and the channel semiconductor layer.

### Claim 16 (depends on 11)

The memory device using the semiconductor element according to claim 11, wherein:
when viewed from an axial direction of the semiconductor base, the first gate conductor layer and the second gate conductor layer are opposite and separate from each other while surrounding the second gate insulating layer.

### Claim 17 (depends on 11)

The memory device using the semiconductor element according to claim 11, wherein:
the impact ionization occurs inside the channel semiconductor layer between the first gate conductor layer and the third gate conductor layer, and generates the hole group inside the channel semiconductor layer.

### Claim 18 (depends on 11)

The memory device using the semiconductor element according to claim 11, wherein:
the source line is separated every memory cells arrayed in the column direction, and is arranged parallel to the word line, the first plate line, and the second plate line.

### Claim 19 (depends on 11)

The memory device using the semiconductor element according to claim 11, wherein:
in an all-page erase operation, an all-page selection signal is input to a row decoder circuit, and all the pages are selected and erased.

### Claim 20 (depends on 11)

The memory device using the semiconductor element according to claim 11, wherein:
in the page erase operation, a fixed voltage is applied as a voltage of the source line and the bit line.