# US 12,120,811 B2 · Multi-dielectric printed circuit board

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- Number: US 12,120,811 B2
- Document ID: US12120811B2
- Status: Granted
- Kind: B2
- Application number: 17/133,234
- Filed: 2020-12-23
- Published: 2022-06-23
- Granted: 2024-10-15
- Earliest claimed: 2020-12-23
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Arvind S; Raghavendra Rao; Geejagaaru Krishnamurthy Sandesh
- Web page: https://patentgrep.com/patent/US12120811B2

## CPC

- H05K 1/024: {Dielectric details, e.g. changing the dielectric material around a transmission line}
- H05K 1/0231: {Capacitors or dielectric substances}
- H05K 1/0243: {Printed circuits associated with mounted high frequency components}
- H05K 3/4673: {Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer (similar methods for protective coatings H05K3/28)}
- H05K 3/4688: {Composite multilayer circuits, i.e. comprising insulating layers having different properties (having a special base or central core H05K3/4602)}
- H05K 1/0245: {Lay-out of balanced signal pairs, e.g. differential lines or twisted lines}
- H05K 1/0306: {Inorganic insulating substrates, e.g. ceramic, glass}
- H05K 1/036: {Multilayers with layers of different types}
- H05K 1/0366: {reinforced, e.g. by fibres, fabrics (H05K1/036 takes precedence)}
- H05K 2201/0187: with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
- H05K 2201/068: wherein the coefficient of thermal expansion is important
- H05K 2201/10159: Memory
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A printed circuit board (PCB), comprising a first layer, the first layer comprising a first dielectric material substantially exclusively. The PCB also comprises a second layer, the second layer comprising the first dielectric material within a first region and a second dielectric material within a second region adjacent to first region. The first dielectric material has a first dielectric constant, a first coefficient of thermal expansion (CTE) and a first glass transition temperature (Tg). The second dielectric material has a second dielectric constant, a second CTE and a second Tg. The first dielectric constant is greater than the second dielectric constant. The first CTE is substantially equal to the second CTE; and the first Tg and the second Tg are greater than 150° C.

## Claims

### Claim 1

A printed circuit board (PCB), comprising:
a first layer comprising a first dielectric material substantially exclusively; and
a second layer comprising the first dielectric material within a first region and a second dielectric material within a second region adjacent to the first region, wherein:
the first dielectric material has a first dielectric constant, a first coefficient of thermal expansion (CTE) and a first glass transition temperature (Tg);
the second dielectric material has a second dielectric constant, a second CTE and a second Tg;
the first dielectric constant is a greater than the second dielectric constant;
the first CTE is substantially equal to the second CTE; and
the first Tg and the second Tg are greater than 150° C.

### Claim 2 (depends on 1)

The PCB of claim 1, wherein a first boundary between the first region and the second region extends around a periphery of the second region.

### Claim 3 (depends on 2)

The PCB of claim 2, wherein the first dielectric material is mixed with the second dielectric material at the first boundary.

### Claim 4 (depends on 2)

The PCB of claim 2, wherein a first sidewall of the first region is adjacent to a second sidewall of the second region at the first boundary.

### Claim 5 (depends on 4)

The PCB of claim 4, wherein a first distance between the first sidewall and the second sidewall is between zero and 10 microns.

### Claim 6 (depends on 1)

The PCB of claim 1, wherein the second layer further comprises a third dielectric material within a third region adjacent to the first region.

### Claim 7 (depends on 6)

The PCB of claim 6, wherein a boundary between the first region and the third region extends around a periphery of the third region.

### Claim 8 (depends on 6)

The PCB of claim 6, wherein the third dielectric material has a third dielectric constant that is less than the second dielectric constant, a third Tg that is substantially equal to the first Tg and the second Tg, and a third CTE that is substantially equal to the first CTE and the second CTE.

### Claim 9 (depends on 1)

The PCB of claim 1, wherein a first core layer is between the first layer and the second layer, the first core layer having a first surface and an opposing second surface, wherein a first copper layer is over the first surface and a second copper layer is over the second surface, and wherein the first core layer comprises a fourth dielectric material having a fourth dielectric constant that is less than the first dielectric constant.

### Claim 10 (depends on 9)

The PCB of claim 9, further comprising a third layer, wherein the third layer comprises a fourth region and a fifth region adjacent to the fourth region, and wherein the fourth region comprises a fifth material having a fifth dielectric constant, and the fifth region comprising a sixth material having a sixth dielectric constant.

### Claim 11 (depends on 10)

The PCB of claim 10, wherein a second core layer is between the first layer and the third layer, the second core layer having a third surface and an opposing fourth surface, wherein a third copper layer is over the third surface and a fourth copper layer is over the fourth surface, and wherein the second core layer comprises a seventh dielectric material having a seventh dielectric constant that is less than the first dielectric constant.

### Claim 12 (depends on 1)

The PCB of claim 1, wherein the first dielectric constant is at least 0.3 units greater than the second dielectric constant.

### Claim 13

A system, comprising:
a printed circuit board (PCB) comprising:
a first layer comprising a first dielectric material substantially exclusively; and
a second layer comprising the first dielectric material within a first region and a second dielectric material within a second region adjacent to the first region, wherein:
the first dielectric material has a first dielectric constant, a first coefficient of thermal expansion (CTE) and a first glass transition temperature (Tg);
the second dielectric material has a second dielectric constant, a second CTE and a second Tg;
the first dielectric constant is greater than the second dielectric constant;
the first CTE is substantially equal to the second CTE; and
the first Tg and the second Tg are greater than 150° C.,
a first routing over the first region of the second layer; and
a second routing over the second region of the second layer.

### Claim 14 (depends on 13)

The system of claim 13, wherein the first routing is a first portion of a parallel memory interface routing or a chip package routing that extends over the second region of the second layer.

### Claim 15 (depends on 14)

The system of claim 14, wherein a second portion of the parallel memory interface routing is over the first layer.

### Claim 16 (depends on 13)

The system of claim 13, wherein the second routing is a portion of a HSIO serial interface routing or a chip package routing that extends over the first region of the second layer.

### Claim 17 (depends on 16)

The system of claim 16, wherein the HSIO serial interface routing is a first HSIO serial interface routing, and a second HSIO serial interface routing is over a third region of the second layer.

### Claim 18 (depends on 13)

The system of claim 13, wherein the second layer comprises a third region, wherein the third region comprises a third material having a third dielectric constant that is substantially different from the second dielectric constant.

### Claim 19 (depends on 13)

The system of claim 13, further comprising a third layer, wherein the third layer comprises a fourth region and a fifth region adjacent to the fourth region, and wherein the fourth region comprises a fourth material having the first dielectric constant, and the fifth region comprises a fifth material having the second dielectric constant.

### Claim 20

A method for making a printed circuit board (PCB), comprising:
receiving a PCB layer stack comprising a core, wherein the core comprises a dielectric layer comprising a first dielectric material exclusively, wherein the first dielectric material has a first dielectric constant, and wherein a first conductive layer is over a first side of the first dielectric layer and a second conductive layer is over an opposing second side of the first dielectric layer;
patterning the first conductive layer to form high-speed interface routing comprising a high-speed input/output (HSIO) interface routing and a high-speed parallel interface routing;
laminating a first prepreg sheet comprising the first dielectric material over the first conductive layer, wherein the first prepreg sheet comprises one or more openings; and
riveting a second prepreg sheet in the one or more openings in the first prepreg sheet, wherein the second prepreg sheet has a second dielectric constant that is substantially different than the first dielectric constant.

### Claim 21 (depends on 20)

The method of claim 20, wherein laminating the first prepreg sheet over the first conductive layer comprises aligning the one or more openings over the HSIO interface routing.

### Claim 22 (depends on 20)

The method of claim 20, wherein riveting the second prepreg sheet in the one or more openings comprises driving a plurality of rivets along a peripheral zone of the second prepreg sheet to fasten the second prepreg sheet to the core.

### Claim 23 (depends on 20)

The method of claim 20, further comprising riveting a third prepreg sheet in the one or more openings, wherein riveting the third prepreg sheet comprises driving a plurality of rivets along a peripheral zone of the third prepreg sheet to fasten the third prepreg sheet to the core.