# US 12,120,446 B2 · Imaging device and electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,120,446 B2 - Document ID: US12120446B2 - Status: Granted - Kind: B2 - Application number: 18/008,302 - Filed: 2021-07-12 - Published: 2023-06-08 - Granted: 2024-10-15 - Earliest claimed: 2020-07-24 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Shunsuke Sato; Seiichi Yoneda; Yusuke Negoro; Takeya Hirose; Shunpei Yamazaki - Web page: https://patentgrep.com/patent/US12120446B2 ## CPC - H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components - H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - H04N 25/00: Circuitry of solid-state image sensors [SSIS]; Control thereof - H04N 25/79: Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors - H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} - H10F 39/191: {Photoconductor image sensors} - H10F 39/8037: {the integrated elements comprising a transistor} - H10F 39/809: {of hybrid image sensors} - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract An imaging device that has an image processing function and is capable of operating at high speed is provided. The imaging device has an additional function such as image processing, image data obtained by an imaging operation is binarized in a pixel unit, and a product-sum operation is performed using the binarized data. A memory circuit is provided in the pixel unit and retains a weight coefficient used for the product-sum operation. Thus, an arithmetic operation can be performed without the weight coefficient read from the outside every time, whereby power consumption can be reduced. Furthermore, a pixel circuit, a memory circuit, and the like and a product-sum operation circuit and the like are stacked, so that the lengths of wirings between the circuits can be reduced, and high-speed operation with low power consumption can be performed. ## Claims ### Claim 1 An imaging device comprising: a plurality of pixel blocks, wherein each of the plurality of pixel blocks comprises: a first layer comprising a plurality of pixel circuits and a plurality of first memory circuits; and a second layer comprising a plurality of product-sum operation circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits, wherein the first layer comprises a region overlapping with the second layer, and wherein each of the plurality of pixel circuits and each of the first memory circuits comprises a transistor including a metal oxide in a channel formation region. ### Claim 2 (depends on 1) The imaging device according to claim 1, wherein each of the plurality of product-sum operation circuits, each of the plurality of first binarization circuits, and each of the plurality of second binarization circuits comprises a transistor including silicon in a channel formation region. ### Claim 3 (depends on 1) The imaging device according to claim 1, wherein one of the plurality of pixel circuits is electrically connected to one of the plurality of first binarization circuits. ### Claim 4 (depends on 1) The imaging device according to claim 1, wherein one of the plurality of first binarization circuits is electrically connected to the plurality of product-sum operation circuits. ### Claim 5 (depends on 1) The imaging device according to claim 1, wherein one of the purality of the first memory circuits is electrically connected to the plurality of product-sum operation circuits. ### Claim 6 (depends on 1) The imaging device according to claim 1, wherein one of the plurality of product-sum operation circuits is electrically connected to one of the plurality of second binarization circuits. ### Claim 7 (depends on 1) The imaging device according to claim 1, further comprising a second memory circuit, wherein an input terminal of the second memory circuit is electrically connected to the plurality of second binarization circuits, and wherein an output terminal of the second memory circuit is electrically connected to the plurality of product-sum operation circuits. ### Claim 8 (depends on 7) The imaging device according to claim 7, further comprising a third memory circuit and a third binarization circuit, wherein the third memory circuit is electrically connected to the plurality of product-sum operation circuits through the third binarization circuit. ### Claim 9 (depends on 1) The imaging device according to claim 1, wherein the metal oxide comprises In. ### Claim 10 An imaging device comprising: a plurality of pixel blocks, wherein each of the plurality of pixel blocks comprises: a first layer comprising a plurality of pixel circuits; a second layer comprising a plurality of product-sum operation circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits; and a third layer comprising a plurality of first memory circuits, wherein the first layer comprises a region overlapping with the second layer and a region overlapping with the third layer, and wherein each of the plurality of pixel circuits and each of the first memory circuits comprises a transistor including a metal oxide in a channel formation region. ### Claim 11 (depends on 10) The imaging device according to claim 10, wherein each of the plurality of product-sum operation circuits, each of the plurality of first binarization circuits, and each of the plurality of second binarization circuits comprises a transistor including silicon in a channel formation region. ### Claim 12 (depends on 10) The imaging device according to claim 10, wherein one of the plurality of pixel circuits is electrically connected to one of the plurality of first binarization circuits. ### Claim 13 (depends on 10) The imaging device according to claim 10, wherein one of the plurality of first binarization circuits is electrically connected to the plurality of product-sum operation circuits. ### Claim 14 (depends on 10) The imaging device according to claim 10, wherein one of the plurality of the first memory circuits is electrically connected to the plurality of product-sum operation circuits. ### Claim 15 (depends on 10) The imaging device according to claim 10, wherein one of the plurality of product-sum operation circuits is electrically connected to one of the plurality of second binarization circuits. ### Claim 16 (depends on 10) The imaging device according to claim 10, further comprising a second memory circuit, wherein an input terminal of the second memory circuit is electrically connected to the plurality of second binarization circuits, and wherein an output terminal of the second memory circuit is electrically connected to the plurality of product-sum operation circuits. ### Claim 17 (depends on 16) The imaging device according to claim 16, further comprising a third memory circuit and a third binarization circuit, wherein the third memory circuit is electrically connected to the plurality of product-sum operation circuits through the third binarization circuit. ### Claim 18 (depends on 10) The imaging device according to claim 10, wherein the metal oxide comprises In.