# US 12,120,213 B2 · 100BASE-TX transceiver with transmit clock selected from output clock of clock generator circuit and receive recovered clock of clock and data recovery circuit and associated method

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- Number: US 12,120,213 B2
- Document ID: US12120213B2
- Status: Granted
- Kind: B2
- Application number: 18/073,528
- Filed: 2022-12-01
- Published: 2023-11-30
- Granted: 2024-10-15
- Earliest claimed: 2022-05-30
- Assignees: Airoha Technology Corp.
- Applicants: Airoha Technology Corp.
- Inventors: Chia-Hsing Hsu; Chun-Chia Huang
- Web page: https://patentgrep.com/patent/US12120213B2

## CPC

- H04J 3/0697: {Synchronisation in a packet node}
- H04L 7/0079: {Receiver details}
- H04J 3/0688: {Change of the master or reference, e.g. take-over or failure of the master}
- H04L 12/12: Arrangements for remote connection or disconnection of substations or of equipment thereof
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A 100BASE-TX transceiver includes a receive (RX) circuit, a transmit (TX) circuit, a clock generator circuit, a clock and data recovery (CDR) circuit, and a clock multiplexer circuit. The RX circuit receives an input data to generate an RX data. The TX circuit transmits a TX data according to a TX clock, to generate an output data. The clock generator circuit generates an output clock. The CDR circuit generates an RX recovered clock according to the RX data. The clock multiplexer circuit receives the output clock and the RX recovered clock, and outputs the TX clock that is selected from the output clock and the RX recovered clock.

## Claims

### Claim 1

A 100BASE-TX transceiver comprising:
a receive (RX) circuit, arranged to receive an input data to generate an RX data;
a transmit (TX) circuit, arranged to transmit a TX data according to a TX clock, to generate an output data;
a clock generator circuit, arranged to generate an output clock;
a clock and data recovery (CDR) circuit, arranged to generate an RX recovered clock according to the RX data;
a clock multiplexer circuit, arranged to receive the output clock and the RX recovered clock, and output the TX clock that is selected from the output clock and the RX recovered clock; and
a decision logic, arranged to check a media independent interface (MDI) status of the 100BASE-TX transceiver that is set by an automatic media independent interface/media independent interface with crossover (MDI/MDIX) feature, and refer to the MDI status to set a selection control signal of the clock multiplexer circuit.

### Claim 2 (depends on 1)

The 100BASE-TX transceiver of claim 1, wherein when the MDI status of the 100BASE-TX transceiver indicates that one of an MDI port and an MDIX port is used by the 100BASE-TX transceiver, the decision logic sets the selection control signal for instructing the clock multiplexer circuit to output the output clock as the TX clock; and when the MDI status of the 100BASE-TX transceiver indicates that another of the MDI port and the MDIX port is used by the 100BASE-TX transceiver, the decision logic sets the selection control signal for instructing the clock multiplexer circuit to output the RX recovered clock as the TX clock.

### Claim 3 (depends on 1)

The 100BASE-TX transceiver of claim 1,
wherein during a detection phase, the detection logic is further arranged to instruct the clock multiplexer circuit to output the output clock as the TX clock;
the 100BASE-TX transceiver further comprises:
a frequency modulation (FM) control logic, wherein during the detection phase, the FM control logic is enabled to instruct the clock generator circuit to generate the output clock that is frequency modulated according to a pre-defined FM pattern; and during a decision phase following the detection phase, the FM control logic is disabled; and
a detection logic, wherein during the detection phase, the detection logic is arranged to detect frequency change of the RX recovered clock;
wherein during the decision phase, the decision logic is further arranged to compare the frequency change of the RX recovered clock with the pre-defined FM pattern to generate a comparison result, and refer to the comparison result to set the selection control signal of the clock multiplexer circuit.

### Claim 4 (depends on 3)

The 100BASE-TX transceiver of claim 3, wherein when the comparison result indicates that the frequency change of the RX recovered clock matches the pre-defined FM pattern, the decision logic sets the selection control signal for instructing the clock multiplexer circuit to output the output clock as the TX clock; and when the comparison result indicates that the frequency change of the RX recovered clock does not match the pre-defined FM pattern, the decision logic sets the selection control signal for instructing the clock multiplexer circuit to output the RX recovered clock as the TX clock.

### Claim 5

A 100BASE-TX transceiver comprising:
a receive (RX) circuit, arranged to receive an input data to generate an RX data;
a transmit (TX) circuit, arranged to transmit a TX data according to a TX clock, to generate an output data;
a clock generator circuit, arranged to generate an output clock;
a clock and data recovery (CDR) circuit, arranged to generate an RX recovered clock according to the RX data;
a clock multiplexer circuit, arranged to receive the output clock and the RX recovered clock, and output the TX clock that is selected from the output clock and the RX recovered clock; and
a decision logic, arranged to generate a local random number, obtain a random number from a link partner, and compare the local random number with the random number obtained from the link partner to set a selection control signal of the clock multiplexer circuit.

### Claim 6 (depends on 5)

The 100BASE-TX transceiver of claim 5, wherein the local random number is further transmitted to the link partner through an auto-negotiation (AN) Next Page.

### Claim 7 (depends on 5)

The 100BASE-TX transceiver of claim 5, wherein when the local random number is smaller than the random number obtained from the link partner, the decision logic sets the selection control signal for instructing the clock multiplexer circuit to output one of the output clock and the RX recovered clock as the TX clock; and when the local random number is larger than the random number obtained from the link partner, the decision logic sets the selection control signal for instructing the clock multiplexer circuit to output another of the output clock and the RX recovered clock as the TX clock.

### Claim 8 (depends on 5)

The 100BASE-TX transceiver of claim 5, wherein when the local random number is equal to the random number obtained from the link partner, an auto-negotiation (AN) between the 100BASE-TX transceiver and the link partner is restarted.

### Claim 9 (depends on 5)

The 100BASE-TX transceiver of claim 5, wherein the random number is obtained from the link partner through an auto-negotiation (AN) Next Page.

### Claim 10

A 100BASE-TX transceiving method comprising:
receiving an input data to generate a receive (RX) data;
transmitting a transmit (TX) data according to a TX clock, to generate an output data;
performing clock generation to generate an output clock;
performing clock and data recovery (CDR) upon the RX data to generate an RX recovered clock;
performing clock multiplexing upon the output clock and the RX recovered clock to output the TX clock that is selected from the output clock and the RX recovered clock; and
checking a media independent interface (MDI) status that is set by an automatic media independent interface/media independent interface with crossover (MDI/MDIX) feature, and referring to the MDI status to configure the clock multiplexing.

### Claim 11 (depends on 10)

The 100BASE-TX transceiving method of claim 10, further comprising:
during a detection phase, performing the clock multiplexing to output the output clock as the TX clock, performing the clock generation to generate the output clock that is frequency modulated according to a pre-defined FM pattern, and detecting frequency change of the RX recovered clock; and
during a decision phase following the detection phase, performing the clock generation to generate the output clock that is not frequency modulated according to the pre-defined FM pattern, comparing the frequency change of the RX recovered clock with the pre-defined FM pattern to generate a comparison result, and referring to the comparison result to control the clock multiplexing.

### Claim 12 (depends on 11)

The 100BASE-TX transceiving method of claim 11, wherein referring to the comparison result to control the clock multiplexing comprises:
in response to the comparison result indicating that the frequency change of the RX recovered clock matches the pre-defined FM pattern, configuring the clock multiplexing to output the output clock as the TX clock; and
in response to the comparison result indicating that the frequency change of the RX recovered clock does not match the pre-defined FM pattern, configuring the clock multiplexing to output the RX recovered clock as the TX clock.

### Claim 13 (depends on 10)

The 100BASE-TX transceiving method of claim 10, wherein referring to the MDI status to configure the clock multiplexing comprises:
in response to the MDI status indicating that one of an MDI port and an MDIX port is used, configuring the clock multiplexing to output the output clock as the TX clock; and
in response to the MDI status indicating that another of the MDI port and the MDIX port is used, configuring the clock multiplexing to output the RX recovered clock as the TX clock.

### Claim 14

A 100BASE-TX transceiving method comprising:
receiving an input data to generate a receive (RX) data;
transmitting a transmit (TX) data according to a TX clock, to generate an output data;
performing clock generation to generate an output clock;
performing clock and data recovery (CDR) upon the RX data to generate an RX recovered clock;
performing clock multiplexing upon the output clock and the RX recovered clock to output the TX clock that is selected from the output clock and the RX recovered clock; and
generating a local random number;
obtaining a random number from a link partner; and
comparing the local random number with the random number obtained from the link partner to configure the clock multiplexing.

### Claim 15 (depends on 14)

The 100BASE-TX transceiving method of claim 14, wherein the random number is obtained from the link partner through an auto-negotiation (AN) Next Page.

### Claim 16 (depends on 14)

The 100BASE-TX transceiving method of claim 14, wherein the local random number is further transmitted to the link partner through an auto-negotiation (AN) Next Page.

### Claim 17 (depends on 14)

The 100BASE-TX transceiving method of claim 14, wherein comparing the local random number with the random number obtained from the link partner to configure the clock multiplexing comprises:
in response to the local random number being smaller than the random number obtained from the link partner, configuring the clock multiplexing to output one of the output clock and the RX recovered clock as the TX clock; and
in response to the local random number being larger than the random number obtained from the link partner, configuring the clock multiplexing to output another of the output clock and the RX recovered clock as the TX clock.

### Claim 18 (depends on 14)

The 100BASE-TX transceiving method of claim 14, wherein an auto-negotiation (AN) is restarted in response to the local random number being equal to the random number obtained from the link partner.