Sampling circuit

A sampling circuit comprising:

• a first transmission line configured to transmit an input signal;
• a second transmission line configured to transmit a clock signal;
• and
• a plurality of sample-hold circuits that are connected to the first and second transmission lines, the plurality of sample-hold circuits being spaced at a constant line distance, the plurality of sample-hold circuits being configured to sample the input signal supplied from the first transmission line at timing designated by the clock signal supplied from the second transmission line, and hold and output the sampled input signal, wherein:
• the first transmission line transmits the input signal at a first propagation time for each of the constant line distance,
• the second transmission line transmits the clock signal at a second propagation time for each of the constant line distance, the second propagation time being different from the first propagation time, and the second propagation time being equal to a sum of a preset sampling interval and the first propagation time,
• the plurality of sample-hold circuits include respective first semiconductor elements having an input terminal connected to the first transmission line in parallel with respective first input transistors connected to the first transmission line;
• and
• the sampling circuit further comprises first bias supply wiring configured to supply a first bias voltage for adjusting input capacitances of the first semiconductor elements to the first semiconductor elements of the plurality of sample-hold circuits.

A method comprising:

• transmitting, by a first transmission line, an input signal;
• a second transmission line configured to transmit a clock signal;
• and
• sampling, by a plurality of sample-hold circuits, the input signal supplied from the first transmission line at timing designated by the clock signal supplied from the second transmission line, wherein the plurality of sample-hold circuits that are connected to the first and second transmission lines, the plurality of sample-hold circuits being spaced at a constant line distance;
• and
• holding and outputting the sampled input signal, wherein
• the first transmission line transmits the input signal at a first propagation time for each of the constant line distance,
• the second transmission line transmits the clock signal at a second propagation time for each of the constant line distance, the second propagation time being different from the first propagation time, and the second propagation time being a sum of a preset sampling interval and the first propagation time,
• the plurality of sample-hold circuits include respective first input transistors having an input terminal connected to the first transmission line, and
• the method further comprises supplying, by first bias supply wiring, a first bias voltage for adjusting input capacitances of the first input transistors to the first input transistors of the plurality of sample-hold circuits.