Machine-learning error-correcting code controller

A memory control circuit comprising:

• an input control circuit configured to receive a data input signal and a validity signal, and output a status signal;
• an equalization arbitration circuit coupled to the input control circuit and configured to select one of a hard-decision (HD) error-correcting code (ECC) or a soft-decision (SD) ECC for decoding the data input signal based on the status signal and a learned cost function of a machine-learning (ML) neural network;
• a weak scan circuit coupled to the input control circuit and the equalization arbitration circuit and configured to receive an index and output a corresponding bit value based on whether the data input signal matches a valid codeword;
• a weak write circuit coupled to the weak scan circuit and the equalization arbitration circuit and configured to receive the index and the bit value and to output a data output signal;
• a calculation control circuit coupled to the equalization arbitration circuit;
• a configuration management buffer configured to store at least one of HD ECC codewords or SD ECC codewords in accordance with an inverse interleaver;
• a pre-calculation circuit coupled to the configuration management buffer;
• an equalization calculation circuit coupled to the configuration management buffer, the pre-calculation circuit and the calculation control circuit;
• and
• an input emulation circuit coupled to the calculation control circuit and the equalization arbitration circuit, and configured to provide a linear ECC output.