# US 12,119,839 B2 · Digital-to-analog converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,839 B2 - Document ID: US12119839B2 - Status: Granted - Kind: B2 - Application number: 18/076,305 - Filed: 2022-12-06 - Published: 2024-06-06 - Granted: 2024-10-15 - Earliest claimed: 2022-12-06 - Assignees: Winbond Electronics Corp. - Applicants: Winbond Electronics Corp. - Inventors: Ju-An Chiang - Web page: https://patentgrep.com/patent/US12119839B2 ## CPC - H03M 1/808: {using resistors} - H03M 1/687: {Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type} - H03M 1/72: Sequential conversion in series-connected stages (H03M1/68 takes precedence) - H03M 1/742: {using current sources as quantisation value generators} - H03M 1/745: {with weighted currents} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A digital-to-analog converter includes an amplifier, a voltage relaxation circuit, a base current source, a first weighting current source, and at least one second weighting current source. The amplifier receives a reference voltage and a feedback voltage, and generates an output voltage according to the reference voltage and the feedback voltage. The base current source is coupled to an output end of the amplifier through the voltage relaxation circuit, and is configured to generate an adjustable base current. The first weighting current source generates an adjustable first weighting current between a reference ground end and one of a current load and the voltage relaxation circuit according to a first bit of input data. The second weighting current source generates at least one second weighting current according to at least one second bit of the input data. ## Claims ### Claim 1 A digital-to-analog converter, comprising: an amplifier receiving a reference voltage and a feedback voltage, and generating an output voltage according to the reference voltage and the feedback voltage; a voltage relaxation circuit coupled to an output end of the amplifier; a base current source coupled to the output end of the amplifier through the voltage relaxation circuit, and configured to generate a base current that is adjustable; a first weighting current source coupled to the output end of the amplifier through a current load and the voltage relaxation circuit, and generating a first weighting current that is adjustable between the current load or the voltage relaxation circuit and a reference ground end according to a first bit of input data; and at least one second weighting current source coupled to the output end of the amplifier through the voltage relaxation circuit, and generating at least one second weighting current according to at least one second bit of the input data. ### Claim 2 (depends on 1) The digital-to-analog converter according to claim 1, wherein the base current source comprises a variable resistor, and the variable resistor adjusts a resistance value provided according to a first control signal. ### Claim 3 (depends on 1) The digital-to-analog converter according to claim 1, wherein the first weighting current source comprises: a variable resistor configured to generate the first weighting current; and a path selector coupled between the variable resistor, the current load, and the voltage relaxation circuit, and coupling the variable resistor to the current load or the voltage relaxation circuit according to the first bit of the input data. ### Claim 4 (depends on 3) The digital-to-analog converter according to claim 3, wherein the path selector comprises: a first transistor coupled to the variable resistor and the voltage relaxation circuit, and controlled by the first bit of the input data; and a second transistor coupled between the variable resistor and the current load, and controlled by a reverse signal of the first bit of the input data. ### Claim 5 (depends on 3) The digital-to-analog converter according to claim 3, wherein the variable resistor receives a second control signal, and adjusts a resistance value provided according to the second control signal. ### Claim 6 (depends on 1) The digital-to-analog converter according to claim 1, wherein the base current source adjusts the base current so that an initial voltage of the output voltage is equal to a target initial voltage, wherein the initial voltage is equal to the output voltage generated by the digital-to-analog converter according to minimum input data. ### Claim 7 (depends on 6) The digital-to-analog converter according to claim 6, wherein the first weighting current source adjusts the first weighting current so that a final voltage of the output voltage is equal to a target final voltage, wherein the final voltage is equal to the output voltage generated by the digital-to-analog converter according to maximum input data. ### Claim 8 (depends on 1) The digital-to-analog converter according to claim 1, wherein the first bit is a most significant bit of the input data. ### Claim 9 (depends on 1) The digital-to-analog converter according to claim 1, wherein the voltage relaxation circuit comprises: a resistor having a first end coupled to the output end of the amplifier; a first transistor controlled by a reference ground voltage; and a second transistor coupled in series with the first transistor between the resistor and the base current source, and controlled by a bias voltage to generate the feedback voltage at an endpoint coupled to the base current source. ### Claim 10 (depends on 1) The digital-to-analog converter according to claim 1, wherein the amplifier comprises: a differential pair receiving the reference voltage and the feedback voltage; an active load coupled to the differential pair; a current source coupled to the differential pair; and an output stage circuit coupled to a differential output end of the differential pair, and generating the output voltage according to the base current, the first weighting current, and the at least one second weighting current. ### Claim 11 (depends on 1) The digital-to-analog converter according to claim 1, further comprising: an encoder/decoder configured to provide the first bit and the at least one second bit of the input data. ### Claim 12 (depends on 1) The digital-to-analog converter according to claim 1, wherein the at least one second weighting current source comprises: a first transistor coupled to the voltage relaxation circuit, and controlled by each of the at least one second bit of the input data; and at least one second transistor coupled in series with the first transistor between the voltage relaxation circuit and a reference ground end, and controlled by at least one bias voltage. ### Claim 13 (depends on 1) The digital-to-analog converter according to claim 1, wherein the first weighting current source comprises a plurality of first sub-weighting current sources, and the first sub-weighting current sources are jointly coupled to the voltage relaxation circuit and the current load and jointly generate the first weighting current. ### Claim 14 (depends on 13) The digital-to-analog converter according to claim 13, wherein the first sub-weighting current sources have the same circuit structure. ### Claim 15 (depends on 13) The digital-to-analog converter according to claim 13, wherein a first sub-weighting current generated by each of the first sub-weighting current sources is 2N times each of the at least one second weighting current, where N is a positive integer.